S19203CBI20 Applied Micro Circuits Corporation, S19203CBI20 Datasheet

S19203CBI20

Manufacturer Part Number

S19203CBI20

Description

Manufacturer

Applied Micro Circuits Corporation

Datasheet

1.S19203CBI20.pdf (3 pages)

Specifications of S19203CBI20

Lead Free Status / Rohs Status

Not Compliant

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Company:

Bonase Electronics (HK) Co., Limited

Part Number:

S19203CBI20

Manufacturer:

AMCC

Quantity:

1 045

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The Hudson is a fully integrated, Variable Rate Digital Wrapper Framer/Deframer, Performance Monitor, and Forward Error Correction (FEC)

device supporting the Digital Wrapper transmission standards for OTU1, OTU2, ODU1, ODU2, OPU1, and OPU2 as specified in G.709. The

Hudson implements Performance Monitoring and overhead processing functions on the Digital Wrapper overhead bytes. In addition, the

device contains SONET/SDH Performance Monitoring to verify the validity of the SONET/SDH OC-192 client data. The device can operate

from a low rate of 6.25 MHz to a high rate of 693.483 MHz. Data entering and leaving the chip can be optionally deframed and framed,

descrambled and scrambled, and decoded and encoded with forward error correction information.

• Core logic runs on a 1.8 V power supply to reduce power con-

• Two independent 16-bit parallel LVDS input and output ports at

• Datapath options: Configurable as two completely independent

• Supports SONET OC-192 Performance Monitoring at the input of

• Supports G.709 “Interfaces for the optical transport network

• ON/OFF control of Reed-Solomon (255,239) FEC Encoding/

HUDSON 2.0

Variable Rate Digital Wrapper Framer/Deframer, PM, and FEC Device

FINAL/PRODUCTION RELEASE Information - The information contained in this

document is about a product in its fully tested and characterized phase. All fea-

tures described herein are supported. Contact AMCC for updates to this docu-

ment and the latest product status.

sumption and LVCMOS I/O are 3.3 V compatible.

up to 693.483 MHz (11.096 Gbps).

data stream for full duplex operation. Configurable as a single

data stream for regenerator operation with dual redundant I/O for

optional protection switching. Either input port can be directly

connected to either output port for loopback testing or bypass

operation.

the encoder side and at the output of the decoder side.

(OTN)” standard including specified frame structure, all overhead

monitoring and processing, Maintenance signals, synchronous

and asynchronous mapping and demapping.

Decoding and error correction.

D U P L E X IN [1 5:0 ]

D E C R X C L K _ D IV

D E C O D E IN [1 5 :0 ]

D U P R X C L K

D U P R X C L K _ D IV

D E C R X C LK

E N C _ D R P _ S F P

E N C _D R P C L K

E N C _ D R P [7 :0 ]

E N C _ D R P _ F P

R X _ O H _ D A T A [7 :0 ]

H u d s o n 2 .0

R X _ O H _ C L K

D R O P S F P

D R O P F P

D U P IN

D e m u x

1 :8

D iv id e r

D e m u x

C lo c k

D E C

1 :8

D iv id e r

C lo c k

IN P U T _P O R T _S W A P

IN P U T _ P O R T _S W A P

D U P O H

F ra m e r

D EC _IN _S E L[1 :0]

Empowering Intelligent Optical Networks

D E C O H

F ram er

S O N E T

E N C

P M

0 0,10

G e n e ra to r

M o n/D ro p

D e s c ra m

& S C /O H

P a tte rn

Figure 1: Block Diagram

O C H

M o n /D ro p

D ec o d e r

D E C O H

D e c o d e (D E C ) S id e

E n co d e (E N C ) S id e

F E C

PA T _G E N _ O N

E N C _IN _ SE L

Applications

• Support for System test and diagnostics: internal BER generator,

• Four programmable integer clock dividers to simplify clock gener-

• Support for signal aggregation to higher rates via chip synchroni-

• General Purpose Processor Interface: Gluess interface to

• Low power: 0.18 micron CMOS technology.

PRBS pattern generator and pattern analyzer for bit error rate

testing capability.

ation.

zation feature.

MPC860, 25 MHz to 50 MHz bus speed. Also compatible with

Intel microprocessor bus via Busmode selector.

M a tch

F IF O

R a te

• 10 Gigabit Digital Wrapper Performance Monitor and Framer

• Protocol Independent DWDM Metropolitan Area Networks

• Optical Cross-connects

• OC-192 Port interface

• Fiber optic terminators, repeaters, and test equipment

M a tc h

F IF O

R a te

S c ra m b le r

A n a ly z e r

D E C O H

P a tte rn

In s &

Part Number S19203CBI20, Revision 1.3, May 2003

E N C O H

E n c o d e r

F ra m e

G e n &

S O N E T

F E C

A d d

D E C

P M

B u ffe r

S y n c

01, 11

0 0, 01

E N C _O U T _ SE L [1:0]

D U P_ O U T _S E L[1:0]

O U T P U T _P O R T _S W A P

O U T P U T _ PO R T _ S W AP

T X _ O H _ D A T A [7 :0]

T X _ O H _ C L K

T X _ O H _ IN S

D E C _ IN S _S F P

D E C _ IN S C L K

D E C _ IN S _ E N

D E C _ IN S _ F P

D E C IN S [7 :0 ]

IN S S F P

IN S F P

U T 1 :8

D iv id e r

D U P O

C lo c k

M u x

D iv id e r

C lo c k

E N C

M u x

8 :1

D U P L E X O U T [1 5 :0 ]

E N C D A T A O U T [1 5 :0 ]

Product Brief

D U P T X C L K _ O U T

D U P T X C LK _ D IV

E N C T X C L K _ D IV

E N C T X C L K

Related parts for S19203CBI20

S19203CBI20 Summary of contents

Page 1

... Optical Cross-connects • OC-192 Port interface • Fiber optic terminators, repeaters, and test equipment Figure 1: Block Diagram _IN _S E L ram tch & n tte _IN Empowering Intelligent Optical Networks Product Brief Part Number S19203CBI20, Revision 1.3, May 2003 L[1: tte 01 & ffe & ...

Page 2

... FEC decoding and encoding may be disabled individually. Figure 2: Full-Duplex Configuration DeMUX ENCODER (S3092) S19203 MUX OTX DECODER (S3091) Figure 3: Typical Edge Application Empowering Intelligent Optical Networks Product Brief Part Number S19203CBI20, Revision 1.3, May 2003 MUX OTX (S3091) FEC Coded Ring DeMUX ORX (S3092 ...

Page 3

... DeM UX (AM CC S3092) SPARE Figure 5: Se;f-Healing BLSR FEC Encoded Network S19203 DEC ENC ENC DEC S19203 Empowering Intelligent Optical Networks Product Brief Part Number S19203CBI20, Revision 1.3, May 2003 PRIM ARY M UX OTX (AM CC S3091 OTX (AM CC S3091) SPARE To Network Encode Out ...

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