MACH210-15JC Lattice, MACH210-15JC Datasheet - Page 41

• Manufacturer Part Number: MACH210-15JC
• Description: CPLD MACH 2 Family 64 Macro Cells 66.6MHz EECMOS Technology 5V 44-Pin PLCC
• Manufacturer: Lattice

Specifications of MACH210-15JC

• Package: 44PLCC
• Family Name: MACH 2
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.6 MHz
• Number Of Product Terms Per Macro: 16
• Memory Type: EEPROM
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

f
The parameter f
the device is guaranteed to operate. Because the flexi-
bility inherent in programmable logic devices offers a
choice of clocked flip-flop designs, f
three types of synchronous designs.
The first type of design is a state machine with feedback
signals sent off-chip. This external feedback could go
back to the device inputs, or to a second device in a
multi-chip state machine. The slowest path defining the
period is the sum of the clock-to-output time and the in-
put setup time for the external signals (t
ciprocal, f
feedback or in conjunction with an equivalent speed de-
vice. This f
The second type of design is a single-chip state ma-
chine with internal feedback only. In this case, flip-flop
inputs are defined by the device inputs and flip-flop out-
puts. Under these conditions, the period is limited by the
internal delay from the flip-flop outputs through the inter-
nal feedback and logic to the flip-flop inputs. This f
designated “f
good example of this type of design; therefore, this pa-
rameter is sometimes called “f
MAX
PARAMETERS
f
MAX
MAX
No Feedback; 1/(t
MAX
LOGIC
LOGIC
t
, is the maximum frequency with external
t
MAX
S
S
is designated “f
f
MAX
MAX
internal”. A simple internal counter is a
External; 1/(t
is the maximum clock rate at which
S
+ t
REGISTER
REGISTER
MAX
CNT.
H
S
) or 1/(t
CLK
CLK
+ t
external.”
”
CO
MAX
t
CO
)
MACH210-7/10/12/15/20, Q-12/15/20
WH
S
is specified for
+ t
+ t
CO
WL
). The re-
)
MAX
(SECOND
t
is
S
CHIP)
The third type of design is a simple data path applica-
tion. In this case, input data is presented to the flip-flop
and clocked through; no feedback is employed. Under
these conditions, the period is limited by the sum of the
data setup time and the data hold time (t
a lower limit for the period of each f
mum clock period (t
clock period determines the period for the third f
ignated “f
For devices with input registers, one additional f
rameter is specified: f
feedback, it is calculated the same way as f
back. The minimum period will be limited either by the
sum of the setup and hold times (t
the clock widths (t
mally the limiting parameters, so that f
as 1/(t
isters are use in the same path, the overall frequency will
be limited by t
All frequencies except f
other measured AC parameters. f
ured directly.
WICL
t
SIR
MAX
+ t
WICH
f
no feedback.”
MAXIR
ICS
REGISTER
LOGIC
t
). Note that if both input and output reg-
.
HIR
WICL
CLK
; 1/(t
WH
+ t
MAXIR
f
SIR
MAX
MAX
WICH
+ t
+ t
. Because this involves no
WL
Internal (f
internal are calculated from
). The clock widths are nor-
HIR
). Usually, this minimum
) or 1/(t
SIR
REGISTER
MAX
MAX
CNT
+ t
LOGIC
CLK
internal is meas-
WICL
HIR
MAXIR
S
type is the mini-
)
+ t
) or the sum of
H
+ t
MAX
). However,
is specified
14128I-24
WICH
MAX
no feed-
MAX
)
, des-
pa-
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