MACH210-15JC Lattice, MACH210-15JC Datasheet - Page 44

• Manufacturer Part Number: MACH210-15JC
• Description: CPLD MACH 2 Family 64 Macro Cells 66.6MHz EECMOS Technology 5V 44-Pin PLCC
• Manufacturer: Lattice

Specifications of MACH210-15JC

• Package: 44PLCC
• Family Name: MACH 2
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 66.6 MHz
• Number Of Product Terms Per Macro: 16
• Memory Type: EEPROM
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

POWER-UP RESET
The MACH devices have been designed with the capa-
bility to reset during system power-up. Following power-
up, all flip-flops will be reset to LOW. The output state
will depend on the logic polarity. This feature provides
extra flexibility to the designer and is especially valuable
in simplifying state machine initialization. A timing dia-
gram and parameter table are shown below. Due to the
synchronous operation of the power-up reset and the
44
Parameter
Symbol
t
t
PR
t
WL
S
Registered
Output
Power
Clock
Parameter Descriptions
Power-Up Reset Time
Input or Feedback Setup Time
Clock Width LOW
4 V
MACH210-7/10/12/15/20, Q-12/15/20
Power-Up Reset Waveform
t
PR
wide range of ways V
conditions are required to insure a valid power-up reset.
These conditions are:
1. The V
2. Following reset, the clock input must not be driven
from LOW to HIGH until all applicable input and
feedback setup times are met.
t
WL
CC
t
S
rise must be monotonic.
CC
can rise to its steady state, two
See
Switching
Characteristics
14128I-26
Max
10
V
CC
Unit
s