TE28F800C3TA90 Intel, TE28F800C3TA90 Datasheet - Page 17

• Manufacturer Part Number: TE28F800C3TA90
• Description: Flash Mem Parallel 3V/3.3V 8M-Bit 512K x 16 90ns 48-Pin TSOP
• Manufacturer: Intel

Specifications of TE28F800C3TA90

• Package: 48TSOP
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Top
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 15
• Support Of Common Flash Interface: Yes
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

3.0
3.1
3.1.1
3.1.2
3.1.3
Datasheet
Device Operations
The C3 device uses a CUI and automated algorithms to simplify Program and Erase operations.
The CUI allows for 100% CMOS - level control inputs and fixed power supplies during erasure and
programming.
The internal WSM completely automates Program and Erase operations while the CUI signals the
start of an operation and the status register reports device status. The CUI handles the WE#
interface to the data and address latches, as well as system status requests during WSM operation.
Bus Operations
The C3 device performs read, program, and erase operations in - system via the local CPU or
microcontroller. Four control pins (CE#, OE#, WE#, and RP#) manage the data flow in and out of
the flash device.
Read
When performing a read cycle, CE# and OE# must be asserted; WE# and RP# must be deasserted.
CE# is the device selection control; when active low, it enables the flash memory device. OE# is
the data output control; when low, data is output on DQ[15:0]. See
Waveform” on page
Write
A write cycle occurs when both CE# and WE# are low; RP# and OE# are high. Commands are
issued to the Command User Interface (CUI). The CUI does not occupy an addressable memory
location. Address and data are latched on the rising edge of the WE# or CE# pulse, whichever
occurs first. See
Output Disable
With OE# at a logic - high level (V
high - impedance state.
Table 5.
Bus Operations
Figure 9, “Write Operations Waveform” on page
Table 5 on page 17
Read
Write
Output Disable
Standby
Reset
NOTE: X = Don’t Care (V
42.
Mode
IH
), the device outputs are disabled. DQ[15:0] are placed in a
summarizes these bus operations.
IL
Intel
or V
RP#
V
V
V
V
V
IH
£
IH
IH
IH
IH
IL
)
Advanced+ Boot Block Flash Memory (C3)
CE#
V
V
V
V
X
IH
IL
IL
IL
OE#
47.
V
V
V
X
X
Figure 8, “Read Operation
IH
IH
IL
WE#
V
V
V
X
X
IH
IH
IL
DQ[15:0]
High-Z
High-Z
High-Z
D
D
OUT
IN
17