TE28F800C3TA90 Intel, TE28F800C3TA90 Datasheet - Page 26

• Manufacturer Part Number: TE28F800C3TA90
• Description: Flash Mem Parallel 3V/3.3V 8M-Bit 512K x 16 90ns 48-Pin TSOP
• Manufacturer: Intel

Specifications of TE28F800C3TA90

• Package: 48TSOP
• Density: 8 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Top
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 15
• Support Of Common Flash Interface: Yes
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

Intel
26
NOTE: See
SR[7] WRITE STATE MACHINE STATUS (WSMS)
SR[6] = ERASE - SUSPEND STATUS (ESS)
SR[5] = ERASE STATUS (ES)
SR[4] = PROGRAM STATUS (PS)
SR[3] = V
SR[2] = PROGRAM SUSPEND STATUS (PSS)
SR[1] = BLOCK LOCK STATUS
aborted.
SR[0] = RESERVED FOR FUTURE ENHANCEMENTS (R)
NOTE: A Command-Sequence Error is indicated when SR[4], SR[5], and SR[7] are set.
1 = Ready
0 = Busy
1 = Erase Suspended
0 = Erase In Progress/Completed
1 = Error In Block Erase
0 = Successful Block Erase
1 = Error in Programming
0 = Successful Programming
1 = V
0 = V
1 = Program Suspended
0 = Program in Progress/Completed
1 = Prog/Erase attempted on a locked block; Operation
0 = No operation to locked blocks
(HEX)
Code
WSMS
10
00
Table 8.
Table 9.
£
PP
PP
7
Advanced+ Boot Block Flash Memory (C3)
OK
Low Detect, Operation Abort
PP
STATUS (VPPS)
Appendix A, “Write State Machine States”
Alt. Prog Set-Up
Device Mode
Reserved
Command Codes and Descriptions
Status Register Bit Definition
Invalid/
ESS
6
Operates the same as Program Set - up command. (See 0x40/Program Set-Up)
Unassigned commands should not be used. Intel reserves the right to redefine these codes for
future functions.
ES
5
PS
4
for mode transition information.
Check Write State Machine bit first to determine Word Program
or Block Erase completion, before checking program or erase-
status bits.
When Erase Suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set to “1” until
an Erase Resume command is issued.
When this bit is set to “1,” WSM has applied the max. number
of erase pulses to the block and is still unable to verify
successful block erasure.
When this bit is set to “1,” WSM has attempted but failed to
program a word/byte.
The V
V
Program or Erase command sequences have been entered,
and informs the system if V
V
WSM. The V
feedback between V
When Program Suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
until a Program Resume command is issued.
If a Program or Erase operation is attempted to one of the
locked blocks, this bit is set by the WSM. The operation
specified is aborted and the device is returned to read status
mode.
This bit is reserved for future use and should be masked out
when polling the status register.
PP
PP
Command Description
VPPS
level. The WSM interrogates V
is also checked before the operation is verified by the
PP
3
status bit does not provide continuous indication of
PP
status bit is not guaranteed to report accurate
PPLK
PSS
2
and V
NOTES:
PP
has not been switched on. The
PP1
PP
Min.
BLS
level only after the
1
Datasheet
R
0