ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 100
ZL50110GAG
Manufacturer Part Number
ZL50110GAG
Description
CESoP Processor 552-Pin BGA Tray
Manufacturer
Zarlink
Datasheet
1.ZL50110GAG.pdf
(113 pages)
Specifications of ZL50110GAG
Package
552BGA
Maximum Data Rate
1000 Mbps
Transmission Media Type
Fiber Optic
Power Supply Type
Analog
Typical Supply Current
950(Max) mA
Typical Operating Supply Voltage
1.8 V
Minimum Operating Supply Voltage
1.65 V
Maximum Operating Supply Voltage
1.95 V
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11.9
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
SYSTEM_CLK Frequency
SYSTEM_CLK accuracy
(synchronous master mode)
SYSTEM_CLK accuracy
(synchronous slave mode and
asynchronous mode)
System Function Port
The system clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for a
short duration while network synchronisation is temporarily disrupted. Drift on the system clock directly affects the Holdover
Mode accuracy. Note that the absolute system clock accuracy does not affect the Holdover accuracy, only the change in the
system clock (SYSTEM_CLK) accuracy while in Holdover. For example, if the system clock oscillator has a temperature
coefficient of 0.1 ppm/ºC, a 10ºC change in temperature while the DPLL is in will result in a frequency accuracy offset of
1ppm. The intrinsic frequency accuracy of the DPLL Holdover Mode is 0.06 ppm, excluding the system clock drift.
The system clock frequency affects the operation of the DPLL in free-run mode. In this mode, the DPLL provides timing and
synchronisation signals which are based on the frequency of the accuracy of the master clock (i.e. frequency of clock output
equals 8.192 MHz ± SYSTEM_CLK accuracy ± 0.005 ppm).
The absolute SYSTEM_CLK accuracy must be controlled to ± 30 ppm in synchronous master mode to enable the internal
DPLL to function correctly.
In asynchronous mode and in synchronous slave mode the DPLL is not used. Therefore the tolerance on SYSTEM_CLK may
be relaxed slightly.
The quality of SYSTEM_CLK, or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery
performance. See Section 6.3.
Parameter
Symbol
CLK
CLK
CLK
Table 43 - System Clock Timing
ACS
ACA
FR
ZL50110/11/12/14
Zarlink Semiconductor Inc.
Min.
-
-
-
100
Typ.
100
-
-
Max.
±200
±30
-
Units
MHz
ppm
ppm
Note 1, Note 2
and Note 5
Note 3
Note 4
Data Sheet
Notes
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