ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 68

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

7.0
7.1
The following lists the intrinsic processing latency of the ZL50110/11/12/14, regardless of the number of active
channels or contexts.
•
•
•
•
End-to-end latency may be estimated as the transmit latency + packet network latency + receive latency. The
transmit latency is the sum of the transmit processing and the number of frames per packet x 125 μs. The receive
latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to
compensate for packet network PDV.
The ZL50110/11/12/14 is capable of creating an extremely low latency connection, with end to end delays of less
than 0.5 ms, depending on user configuration.
7.2
The ZL50110/11/12/14 devices support loopback of the TDM circuits and the circuit emulation packets.
TDM loopback is achieved by first packetizing the TDM circuit as normal via the TDM Interface and Payload
Assembly blocks. The packetized data is then routed by the Task Manager back to the same TDM port via the TDM
Formatter and TDM Interface.
Loopback of the emulated services is achieved by redirecting classified packets from the Packet Receive blocks,
back to the packet network. The Packet Transmit blocks are setup to strip the original header and add a new
header directing the packets back to the source.
7.3
The control processor can generate packets directly, allowing it to use the network for out-of-band communications.
This can be used for transmission of control data or network setup information, e.g., routing information. The host
interface can also be used by a local resource for network transmission of processed data.
The device supports dual address DMA transfers of packets to and from the CPU memory, using the host's own
DMA controller. Table 27 illustrates the maximum bandwidths achievable by an external DMA master.
Note 1:
Note 2:
Note 3:
TDM to Packet transmission processing latency less than 125 μs
Packet to TDM transmission processing latency less than 250 μs (unstructured)
Packet to TDM transmission processing latency less than 250 μs (structured, more than 16 channels in
context)
Packet to TDM transmission processing latency less than 375 μs (structured, 16 or less channels in context)
Latency
Loopback Modes
Host Packet Generation
System Features
Maximum bandwidths are the maximum the ZL50110/11/12/14 devices can transfer under host control, and assumes only
minimal packet processing by the host.
Combined figures assume the same amount of data is to be transferred each way.
DMA with external memory must use single packet mode. Refer to ZL5011x Design Manual for details.
ZL50110/11/12/14 to CPU only
ZL50110/11/12/14 to CPU only
CPU to ZL50110/11/12/14 only
CPU to ZL50110/11/12/14 only
Combined
Combined
DMA Path
2
2
Table 27 - DMA Maximum Bandwidths
ZL50110/11/12/14
Zarlink Semiconductor Inc.
68
Packet Size
>1000 bytes
>1000 bytes
>1000 bytes
60 bytes
60 bytes
60 bytes
Max Bandwidth Mbps
11 (5.5 each way)
58 (29 each way)
6.7
50
60
43
1
Data Sheet