ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 33

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

3.3
For the ZL50111 and ZL50112 variants the packet interface is capable of either 3 MII interfaces, 2 redundant GMII
interfaces or 2 redundant TBI (1000 Mbps) interfaces. The TBI interface is a PCS interface supported by an
integrated 1000BASE-X PCS module. The ZL50110 and ZL50114 variants have either 2 MII interfaces, 2 redundant
GMII interfaces or 2 redundant TBI (1000 Mbps) interfaces. When the packet interface is programmed for PCS/TBI
mode, by default the hardware will not enable auto-negotiation. The TBI auto-negotiation must be done by
application software. Ports 2 and 3 are not available on the ZL50110 and ZL50114 devices.
NOTE: In GMII/TBI mode only 1 GMAC port may be used to receive data. The second GMAC port is for
redundancy purposes only.
Data for all three types of packet switching is based on Specification IEEE Std. 802.3 - 2000. The table below
highlights the valid Ethernet interface combinations:
Note: Port 2 and Port 3 can not be used to receive data simultaneously, they are mutually exclusive for packet
reception. They may both be used for packet transmission if required.
The ZL50110/11/12/14 will not take action when receiving a PAUSE frame. It will not pause the transmission of
traffic. It is normally not required to stop CESoP traffic because it is generally constant bit rate and time sensitive. If
necessary, the limiting of egress non-CESoP traffic may be done external to the ZL50110/11/12/14 (e.g. in an
Ethernet switch).
Table 8 maps the signal pins used in the MII interface to those used in the GMII and TBI interface. Table 9 shows
MII Management Interface Package Ball Definition. Table 10, Table 11, Table 12, and Table 13 show respectively
the MII Port 0, Port 1, Port 2 and Port 3 Interface Package Ball Definition.
All Packet Interface signals are 5 V tolerant, and all outputs are high impedance while System Reset is LOW.
Note 1:
Note 2:
Note 3:
MII Port 0
Packet Interfaces
GE
GE
GE
FE
FE
FE
*ZL50111/112 only
**ZL50111 only
***Standby only
MII Port 1
Mn_LINKUP_LED
Mn_ACTIVE_LED
GE***
Table 8 - Packet Interface Signal Mapping - MII to GMII/TBI
Mn_RXCLK
FE
FE
FE
--
--
MII
-
-
MII Port 2*
FE
FE
--
--
--
--
ZL50110/11/12/14
Zarlink Semiconductor Inc.
Mn_GIGABIT_LED
Mn_LINKUP_LED
Mn_ACTIVE_LED
Mn_REFCLK
Mn_RXCLK
MII Port 3**
GMII
33
FE
FE
--
--
--
--
Mn_GIGABIT_LED
Mn_LINKUP_LED
Mn_ACTIVE_LED
Mn_REFCLK
TBI (PCS)
Mn_RBC0
Data Sheet