ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 46

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

CPU_OE
CPU_TS_ALE
CPU_SDACK1
CPU_SDACK2
CPU_CLK
Signal
Table 15 - CPU Interface Package Ball Definition (continued)
I/O
I
I
I
I
I
AE14
AE15
AF15
AD15
AC14
ZL50110/11/12/14
Package Balls
Zarlink Semiconductor Inc.
46
CPU Output Enable.
Synchronously asserted with respect to
CPU_CLK rising edge, and active low.
Used for CPU reads from the processor
to registers within the ZL50110/11/12/14.
Asserted one clock cycle after
CPU_TS_ALE. Must be asserted with
CPU_CS to asynchronously enable the
CPU_DATA output during a read,
including DMA read.
Synchronous input with rising edge of
CPU_CLK.
Latch Enable (ALE), active high signal.
Asserted with CPU_CS, for a single
clock cycle.
CPU/DMA 1 Acknowledge Input. Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL50110/11/12/14 for a DMA write
transaction. Only used for DMA
transfers, not for normal register access.
CPU/DMA 2 Acknowledge Input Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL50110/11/12/14 for a DMA read
transaction. Only used for DMA
transfers, not for normal register access.
CPU PowerQUICC™ II Bus Interface
clock input. 66 MHz clock, with minimum
of 6 ns high/low time. Used to time all
host interface signals into and out of
ZL50110/11/12/14 device.
Description
Data Sheet