ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 76

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

The maximum lock-in range can be programmed up to ±372 ppm regardless of the input frequency. The DPLL will
fail to lock if the source input frequency is absent, if it is not of approximately the correct frequency or if it is too
jittery. See Section 8.7 for further details. The Application Program Interface (API) software that accompanies the
ZL50110/11/12/14 family can be used to automatically set up the DPLL for the appropriate standard requirement.
The DPLL lock-in range can be programmed using the Lock Range register (see ZL50110/11/12/14 Programmers
Model document) in order to extend or reduce the capture envelope. The DPLL provides bit-error-free reference
switching, meeting the specification limits in the Telcordia GR-1244-CORE standard. If Stratum 4/4E accuracy is not
required, it is possible to use a more relaxed system clock tolerance.
The DPLL output consists of three signals; a common clock (comclk), a double-rate common clock (comclkx2), and
a frame reference (8 kHz). These are used to time the internal TDM Interface, and hence the corresponding TDM
infrastructure attached to the interface. The output clock options are either 2.048 Mbps (comclkx2 at 4.096 Mbps)
or 8.192 Mbps (comclkx2 at 16.384 Mbps), determined by setup in the DPLL control register. The frame pulse is
programmable for polarity and width.
8.1.2
In the event of a reference failure resulting in an absence of both the primary and secondary source, the DPLL
automatically reverts to Holdover mode. The last valid frequency value recorded before failure can be maintained
within the Stratum 3 limits of ±0.05 ppm. The hold value is wholly dependent on the drift and temperature
performance of the system clock. For example, a ±32 ppm oscillator may have a temperature coefficient of
±0.1 ppm/°C. Thus a 10°C ambient change since the DPLL was last in the Locking mode will change the holdover
frequency by an additional ±1 ppm, which is much greater than the ±0.05 ppm Stratum 3 specification. If the strict
target of Stratum 3 holdover accuracy is not required, a less restrictive oscillator can be used for the system clock.
Holdover mode is typically used for a short period of time until network synchronisation is re-established.
8.1.3
In freerun mode the DPLL is programmed with a centre frequency, and can output that frequency within the
Stratum 3 limits of ±4.6 ppm. To achieve this the 100 MHz system clock must have an absolute frequency accuracy
of ±4.6 ppm. The centre frequency is programmed as a fraction of the system clock frequency.
8.1.4
It is possible to “power down” the DPLL when it is not in use. For example, an unstructured TDM system, or use of
an external DPLL would mean the internal DPLL could be switched off, saving power. The internal registers can still
be accessed while the DPLL is powered down.
8.2
There are two identical reference monitor circuits, one for the primary and one for the secondary source. Each
circuit will continually monitor its reference, and report the references validity. The validity criteria depends on the
frequency programmed for the reference. A reference must meet all the following criteria to maintain validity:
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The fail flags are independent of the preferred option for primary or secondary operation, will be asserted in the
event of an invalid signal regardless of mode.
The “period in specified range” check is performed regardless of the programmed frequency. Each period
must be within a range, which is programmable for the application. Refer to the ZL50110/11/12/14
programmers model for details.
If the programmed frequency is 1.544 MHz or 2.048 MHz, the “n periods in specified range” check will be
performed. The time taken for n cycles must be within a programmed range, typically with n at 64, the time
taken for consecutive cycles must be between 62 and 66 periods of the programmed frequency.
Reference Monitor Circuit
Holdover Mode
Freerun Mode
Powerdown Mode
ZL50110/11/12/14
Zarlink Semiconductor Inc.
76
Data Sheet