ZL50110GAG Zarlink, ZL50110GAG Datasheet - Page 36

• Manufacturer Part Number: ZL50110GAG
• Description: CESoP Processor 552-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of ZL50110GAG

• Package: 552BGA
• Maximum Data Rate: 1000 Mbps
• Transmission Media Type: Fiber Optic
• Power Supply Type: Analog
• Typical Supply Current: 950(Max) mA
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.65 V
• Maximum Operating Supply Voltage: 1.95 V

M0_COL
M0_RXD[7:0]
M0_RXDV /
M0_RXD[8]
M0_RXER /
M0_RXD[9]
M0_CRS /
M0_Signal_Detect
M0_TXCLK
M0_TXD[7:0]
Signal
Table 10 - MII Port 0 Interface Package Ball Definition (continued)
I/O
I D
I U
I D
I D
I D
I U
O
Y25
[7]
[6]
[5]
[4]
V25
V26
U25
U24
[7]
[6]
[5]
[4]
W25
W24
U23
V21
W23
W22
V24
Y23
Package Balls
ZL50110/11/12/14
Zarlink Semiconductor Inc.
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
MII Port 0
36
W26
U22
Y26
AA26
AA23
W21
Y22
AA22
GMII/MII - M0_COL.
Collision Detection. This signal is
independent of M0_TXCLK and
M0_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
Receive Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M0_RXCLK (GMII/MII) or the rising
edges of M0_RBC0 and M0_RBC1 (TBI).
GMII/MII - M0_RXDV
Receive Data Valid. Active high. This
signal is clocked on the rising edge of
M0_RXCLK. It is asserted when valid data
is on the M0_RXD bus.
TBI - M0_RXD[8]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
GMII/MII - M0_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M0_RXDV is asserted. Can be used
in conjunction with M0_RXD when
M0_RXDV signal is de-asserted to indicate
a False Carrier.
TBI - M0_RXD[9]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
GMII/MII - M0_CRS
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active
high.
TBI - M0_Signal Detect
Similar function to M0_CRS.
MII only - Transmit Clock
Accepts the following frequencies:
Transmit Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M0_TXCLK (MII) or the rising edge
of M0_GTXCLK (GMII/TBI).
25.0 MHz
MII
Description
100 Mbps
Data Sheet