DS21Q55N Maxim Integrated Products, DS21Q55N Datasheet - Page 195

• Manufacturer Part Number: DS21Q55N
• Description: Framer E1/J1/T1 3.3V 256-Pin BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q55N

• Package: 256BGA
• Number Of Transceivers: 4
• Standard Framing Format: E1|J1|T1
• Maximum Supply Current: 75(Typ) mA
• Minimum Single Supply Voltage: 3.135 V
• Maximum Single Supply Voltage: 3.465 V

DS21Q55 Quad T1/E1/J1 Transceiver
29.
FRACTIONAL T1/E1 SUPPORT
The DS21Q55 can be programmed to output gapped clocks for selected channels in the receive and
transmit paths to simplify connections into a USART or LAPD controller in fractional T1/E1 or ISDN-
PRI applications. The receive and transmit paths have independent enables. Channel formats supported
include 56kbps and 64kbps. This is accomplished by assigning an alternate function to the RCHCLK and
TCHCLK pins. Setting CCR3.0 = 1 causes the RCHCLK pin to output a gapped clock as defined by the
receive fractional T1/E1 function of the PCPR register. Setting CCR3.2 = 1 causes the TCHCLK pin to
output a gapped clock as defined by the transmit fractional T1/E1 function of the PCPR register. CCR3.1
and CCR3.3 can be used to select between 64kbps and 56kbps operation. See Section
4
for details about
programming the per-channel function. In T1 mode no clock is generated at the F-bit position.
When 56kbps mode is selected, the LSB clock in the channel is omitted. Only the seven most significant
bits of the channel have clocks.
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