DS21Q55N Maxim Integrated Products, DS21Q55N Datasheet - Page 47

• Manufacturer Part Number: DS21Q55N
• Description: Framer E1/J1/T1 3.3V 256-Pin BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q55N

• Package: 256BGA
• Number Of Transceivers: 4
• Standard Framing Format: E1|J1|T1
• Maximum Supply Current: 75(Typ) mA
• Minimum Single Supply Voltage: 3.135 V
• Maximum Single Supply Voltage: 3.465 V

DS21Q55 Quad T1/E1/J1 Transceiver
5.2 Interrupt Handling
Various alarms, conditions, and events in the DS21Q55 can cause interrupts. For simplicity, these are all
referred to as events in this explanation. All status registers can be programmed to produce interrupts.
Each status register has an associated interrupt mask register. For example, SR1 (status register 1) has an
interrupt control register called IMR1 (interrupt mask register 1). Status registers are the only sources of
interrupts. On power-up, all writeable registers are automatically cleared. Since bits in the IMRx registers
have to be set = 1 to allow a particular event to cause an interrupt, no interrupts can occur until the host
selects which events are to product interrupts. Since there are potentially many sources of interrupts,
several features are available to help sort out and identify which event is causing an interrupt. When an
interrupt occurs, the host should first read the IIR1 and IIR2 registers (interrupt information registers) to
identify which status register (or registers) is producing the interrupt. Once that is determined, the
individual status register or registers can be examined to determine the exact source. In eight port
configurations, two DS21Q55s can be connected together by the 3-wire ESIB feature. This allows all
eight transceivers to be interrogated by a single CPU port read cycle. The host can determine the
synchronization status, or interrupt status of all eight devices with a single read. The ESIB feature also
allows the user to select from various events to be examined through this method. For more information,
see Section 27.
Once an interrupt has occurred, the interrupt handler routine should set the INTDIS bit (CCR3.6) to stop
further activity on the interrupt pin. After all interrupts have been determined and processed, the interrupt
handler routine should re-enable interrupts by setting the INTDIS bit = 0.
5.3 Status Registers
When a particular event or condition has occurred (or is still occurring in the case of conditions), the
appropriate bit in a status register is set to a 1. All of the status registers operate in a latched fashion. This
means that if an event or condition occurs a bit is set to a 1. It remains set until the user reads that bit. An
event bit is cleared when it is read and it is not set again until the event has occurred again. Condition bits
such as RBL, RLOS, etc., remain set if the alarm is still present.
The user always proceeds a read of any of the status registers with a write. The byte written to the register
informs the DS21Q55 which bits the user wishes to read and have cleared. The user writes a byte to one
of these registers, with a 1 in the bit positions the user wishes to read and a 0 in the bit positions the user
does not wish to obtain the latest information on. When a 1 is written to a bit location, the read register is
updated with the latest information. When a 0 is written to a bit position, the read register is not updated
and the previous value is held. A write to the status registers is immediately followed by a read of the
same register. This write-read scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21Q55 with higher order languages.
Status register bits are divided into two groups, condition bits and event bits. Condition bits are typically
network conditions such as loss-of-sync or all-ones detect. Event bits are typically markers such as the
one-second timer, elastic store slip, etc. Each status register bit is labeled as a condition or event bit.
Some of the status registers have bits for both the detection of a condition and the clearance of the
condition. For example, SR2 has a bit that is set when the device goes into a loss-of-sync state (SR2.0, a
condition bit) and a bit that is set (SR2.4, an event bit) when the loss-of-sync condition clears (goes in
sync). Some of the status register bits (condition bits) do not have a separate bit for the “condition clear”
event but rather the status bit can produce interrupts on both edges, setting and clearing. These bits are
marked as double interrupt bits. An interrupt is produced when the condition occurs and when it clears.
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