DS21Q55N Maxim Integrated Products, DS21Q55N Datasheet - Page 199

• Manufacturer Part Number: DS21Q55N
• Description: Framer E1/J1/T1 3.3V 256-Pin BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q55N

• Package: 256BGA
• Number Of Transceivers: 4
• Standard Framing Format: E1|J1|T1
• Maximum Supply Current: 75(Typ) mA
• Minimum Single Supply Voltage: 3.135 V
• Maximum Single Supply Voltage: 3.465 V

DS21Q55 Quad T1/E1/J1 Transceiver
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK
(Figure
30-2).
Test-Logic-Reset
Upon power-up, the TAP controller is in the Test-Logic-Reset state. The instruction register contains the
IDCODE instruction. All system logic of the device operates normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The instruction register and
test registers remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the
controller into the Capture-DR state and initiates a scan sequence. JTMS HIGH during a rising edge on
JTCLK moves the controller to the Select-IR-Scan state.
Capture-DR
Data can be parallel-loaded into the test data registers selected by the current instruction. If the instruction
does not call for a parallel load or the selected register does not allow parallel loads, the test register
remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if
JTMS is LOW or it goes to the Exit1-DR state if JTMS is HIGH.
Shift-DR
The test data register selected by the current instruction is connected between JTDI and JTDO and shifts
data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the
current instruction is not placed in the serial path, it maintains its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK puts the controller in the Update-DR state, which terminates
the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW puts the controller in
the Pause-DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction retain their previous state. The controller remains in this state while JTMS is LOW. A rising
edge on JTCLK with JTMS HIGH puts the controller in the Exit2-DR state.
Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state puts the controller in the Update-DR state
and terminates the scanning process. A rising edge on JTCLK with JTMS LOW enters the Shift-DR state.
Update-DR
A falling edge on JTCLK while in the Update-DR state latches the data from the shift register path of the
test registers into the data output latches. This prevents changes at the parallel output because of changes
in the shift register.
199 of 237