DS21Q55N Maxim Integrated Products, DS21Q55N Datasheet - Page 211

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DS21Q55N

Manufacturer Part Number
DS21Q55N
Description
Framer E1/J1/T1 3.3V 256-Pin BGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS21Q55N

Package
256BGA
Number Of Transceivers
4
Standard Framing Format
E1|J1|T1
Maximum Supply Current
75(Typ) mA
Minimum Single Supply Voltage
3.135 V
Maximum Single Supply Voltage
3.465 V
Figure 31-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store
Enabled)
Note 1: TCHBLK is programmed to block channel 24 (if the TPCSI bit is set, then the signaling data at TSIG is ignored during channel 24).
Figure 31-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store
Enabled)
Note 1: TSER data in channels 1, 5, 9, 13, 17, 21, 25, and 29 is ignored.
Note 2: TCHBLK is programmed to block channel 31 (if the TPCSI bit is set, then the signaling data at TSIG will be ignored).
Note 3: TCHBLK is forced to 1 in the same channels as TSER is ignored (see Note 1).
Note 4: The F-bit position for the T1 frame is sampled and passed through the transmit-side elastic store into the MSB bit position of channel 1.
TCHBLK
(Normally, the transmit-side formatter overwrites the F-bit position unless the formatter is programmed to pass through the F-bit
position.)
TSYSCLK
TSYSCLK
TCHBLK
TCHCLK
TSSYNC
TCHCLK
TSSYNC
TSER
TSER
TSIG
TSIG
2,3
1
1
CHANNEL 23
CHANNEL 31
CHANNEL 31
CHANNEL 23
A
A
B
B
C/A D/B
C/A D/B
LSB MSB
LSB MSB
211 of 237
CHANNEL 24
CHANNEL 24
CHANNEL 32
CHANNEL 32
A
A
B
B
C/A D/B
C/A D/B
LSB
LSB
F
F MSB
4
CHANNEL 1
CHANNEL 1
CHANNEL 1
CHANNEL 1
A
A

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