XC3164A-4PC84C Xilinx Inc, XC3164A-4PC84C Datasheet

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XC3164A-4PC84C

Manufacturer Part Number
XC3164A-4PC84C
Description
FPGA XC3100A Family 4.5K Gates 224 Cells 227MHz CMOS Technology 5V 84-Pin PLCC
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC3164A-4PC84C

Package
84PLCC
Family Name
XC3100A
Device Logic Units
224
Device System Gates
4500
Number Of Registers
688
Maximum Internal Frequency
227 MHz
Typical Operating Supply Voltage
5 V
Maximum Number Of User I/os
70
Ram Bits
46064
Re-programmability Support
Yes
Dc
97+

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XC3164A-4PC84C
Manufacturer:
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0
November 9, 1998 (Version 3.1)
Features
• Complete line of four related Field Programmable Gate
• Ideal for a wide range of custom VLSI design tasks
• High-performance CMOS static memory technology
• Flexible FPGA architecture
• Unlimited reprogrammability
• Extensive packaging options
• Ready for volume production
November 9, 1998 (Version 3.1)
XC3020A, 3020L, 3120A
XC3030A, 3030L, 3130A
XC3042A, 3042L, 3142A, 3142L
XC3064A, 3064L, 3164A
XC3090A, 3090L, 3190A, 3190L
XC3195A
Array product families
- XC3000A, XC3000L, XC3100A, XC3100L
- Replaces TTL, MSI, and other PLD logic
- Integrates complete sub-systems into a single
- Avoids the NRE, time delay, and risk of conventional
- Guaranteed toggle rates of 70 to 370 MHz, logic
- System clock speeds over 85 MHz
- Low quiescent and active power consumption
- Compatible arrays ranging from 1,000 to 7,500 gate
- Extensive register, combinatorial, and I/O
- High fan-out signal distribution, low-skew clock nets
- Internal 3-state bus capabilities
- TTL or CMOS input thresholds
- On-chip crystal oscillator amplifier
- Easy design iteration
- In-system logic changes
- Over 20 different packages
- Plastic and ceramic surface-mount and pin-grid-
- Thin and Very Thin Quad Flat Pack (TQFP and
- Standard, off-the-shelf product availability
- 100% factory pre-tested devices
- Excellent reliability record
package
masked gate arrays
delays from 7 to 1.5 ns
complexity
capabilities
array packages
VQFP) options
Device
R
Max Logic
Gates
1,500
2,000
3,000
4,500
6,000
7,500
Typical Gate
1,000 - 1,500
1,500 - 2,000
2,000 - 3,000
3,500 - 4,500
5,000 - 6,000
6,500 - 7,500
Range
0
0
CLBs
7*
100
144
224
320
484
64
XC3000 Series
Field Programmable Gate Arrays
(XC3000A/L, XC3100A/L)
Product Description
Additional XC3100A Features
• Ultra-high-speed FPGA family with six members
• High-end additional family member in the 22 X 22 CLB
• 8 mA output sink current and 8 mA source current
• Maximum power-down and quiescent current is 5 mA
• 100% architecture and pin-out compatible with other
• Software and bitstream compatible with the XC3000,
XC3100A combines the features of the XC3000A and
XC3100 families:
• Additional interconnect resources for TBUFs and CE
• Error checking of the configuration bitstream
• Soft startup holds all outputs slew-rate limited during
• More advanced CMOS process
Low-Voltage Versions Available
• Low-voltage devices function at 3.0 - 3.6 V
• XC3000L - Low-voltage versions of XC3000A devices
• XC3100L - Low-voltage versions of XC3100A devices
• Complete Development System
10 x 10
12 x 12
16 x 14
16 x 20
22 x 22
Array
8 x 8
- Schematic capture, automatic place and route
- Logic and timing simulation
- Interactive design editor for design optimization
- Timing calculator
- Interfaces to popular design environments like
- 50-85 MHz system clock rates
- 190 to 370 MHz guaranteed flip-flop toggle rates
- 1.55 to 4.1 ns logic delays
array-size XC3195A device
XC3000 families
XC3000A, and XC3000L families
inputs
initial power-up
Viewlogic, Cadence, Mentor Graphics, and others
User I/Os
Max
120
144
176
64
80
96
Flip-Flops
1,320
256
360
480
688
928
Horizontal
Longlines
16
20
24
32
40
44
Configuration
Data Bits
14,779
22,176
30,784
46,064
64,160
94,984
7-3
7

Related parts for XC3164A-4PC84C

XC3164A-4PC84C Summary of contents

Page 1

R November 9, 1998 (Version 3.1) Features • Complete line of four related Field Programmable Gate Array product families - XC3000A, XC3000L, XC3100A, XC3100L • Ideal for a wide range of custom VLSI design tasks - Replaces TTL, MSI, and ...

Page 2

XC3000 Series Field Programmable Gate Arrays Introduction XC3000-Series Field Programmable Gate Arrays (FPGAs) provide a group of high-performance, high-density, digital integrated circuits. Their regular, extendable, flexible, user-programmable array architecture is composed of a configuration program store plus three types of ...

Page 3

R Improvements in the XC3000A and XC3000L Families The XC3000A and XC3000L families offer the following enhancements over the popular XC3000 family: The XC3000A and XC3000L families have additional inter- connect resources to drive the I-inputs of TBUFs driving horizontal ...

Page 4

XC3000 Series Field Programmable Gate Arrays Detailed Functional Description The perimeter of configurable Input/Output Blocks (IOBs) provides a programmable interface between the internal logic array and the device package pins. The array of Con- figurable Logic Blocks (CLBs) performs user-specified ...

Page 5

R Read or Write Data Figure 3: Static Configuration Memory Cell loaded with one bit of configuration program and con- trols one program selection in the Field Programmable Gate Array. The memory cell outputs Q and Q use ...

Page 6

XC3000 Series Field Programmable Gate Arrays The input-buffer portion of each IOB provides threshold detection to translate external signals applied to the pack- age pin to internal logic levels. The global input-buffer threshold of the IOBs can be programmed to ...

Page 7

R Configurable Logic Block The array of CLBs provides the functional elements from which the user’s logic is constructed. The logic blocks are arranged in a matrix within the perimeter of IOBs. For example, the XC3020A has 64 such blocks ...

Page 8

XC3000 Series Field Programmable Gate Arrays Flexible routing allows use of common or individual CLB clocking. The combinatorial-logic portion of the CLB uses look-up table to implement Boolean functions. Variables selected from the five logic inputs ...

Page 9

R Count Enable Parallel Enable Clock Dual Function of 4 Variables D0 D1 Function of 5 Variables D2 Function of 6 Variables Figure 7: Counter. The modulo-8 binary counter with parallel enable and clock enable uses one combinatorial logic block ...

Page 10

XC3000 Series Field Programmable Gate Arrays Figure 9: Design Editor Locations of interconnect access, CLB control inputs, logic inputs and outputs. The dot pattern represents the available programmable interconnection points (PIPs). Some of the interconnect PIPs are directional. 7-12 R ...

Page 11

R Figure 10: FPGA General-Purpose Interconnect. Composed of a grid of metal segments that may be inter- connected through switch matrices to form networks for CLB and IOB inputs and outputs. Figure 11: Switch Matrix Interconnection Options for Each Pin. ...

Page 12

XC3000 Series Field Programmable Gate Arrays Global Buffer Direct Input * Unbonded IOBs (6 Places) Figure 13: XC3020A Die-Edge IOBs. The XC3020A die-edge IOBs are provided with direct access to adjacent CLBs. 7-14 Global Buffer Inerconnect Alternate Buffer Direct Input ...

Page 13

R Longlines The Longlines bypass the switch matrices and are intended primarily for signals that must travel a long distance, or must have minimum skew among multiple destinations. Longlines, shown in Figure 14, run vertically and horizon- tally the height ...

Page 14

XC3000 Series Field Programmable Gate Arrays Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Three-state buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left ...

Page 15

R A buffer in the upper left corner of the FPGA chip drives a global net which is available to all K inputs of logic blocks. Using the global buffer for a clock signal provides a skew-free, high fan-out, synchronized ...

Page 16

XC3000 Series Field Programmable Gate Arrays Crystal Oscillator Figure 18 also shows the location of an internal high speed inverting amplifier that may be used to implement an on-chip crystal oscillator associated with the auxiliary buffer in the ...

Page 17

R Configuration Initialization Phase An internal power-on-reset circuit is triggered when power is applied. When V reaches the voltage at which portions CC of the FPGA device begin to operate (nominally 2 V), the programmable I/O output buffers ...

Page 18

... function of DONE and RESET timing selected. An additional 8 is Figure Header Program Data Repeated for Each Logic Cell Array in a Daisy Chain X5300_01 XC3090A XC3064A XC3090L XC3064L XC3190A XC3164A XC3190L XC3195A 3,500 to 4,500 5,000 to 6,000 6,500 to 7,500 224 320 484 (16 x 14) (20 x 16) (22 x 22) ...

Page 19

R a synchronous start-up sequence and become operational. See Figure 22. Two CCLK cycles after the completion of loading configuration data, the user I/O pins are enabled as configured. As selected, the internal user-logic RESET is released either one clock ...

Page 20

XC3000 Series Field Programmable Gate Arrays be used to drive the remaining unused routing, as that might affect timing of user nets. Tie can be omitted for quick breadboard iterations where a few additional milliamps of Icc are acceptable. The ...

Page 21

R Special Configuration Functions The configuration data includes control over several spe- cial functions in addition to the normal user logic functions and interconnect. • Input thresholds • Readback disable • DONE pull-up resistor • DONE timing • RESET timing ...

Page 22

XC3000 Series Field Programmable Gate Arrays RESET Timing As with DONE timing, the timing of the release of the inter- nal reset can be controlled to occur either a CCLK cycle before, or after, the outputs going active. See This ...

Page 23

R Configuration Timing This section describes the configuration modes in detail. Master Serial Mode In Master Serial mode, the CCLK output of the lead FPGA drives a Xilinx Serial PROM that feeds the DIN input. Each rising edge of the ...

Page 24

XC3000 Series Field Programmable Gate Arrays CCLK (Output Serial Data In Serial DOUT n – 3 (Output) Description Data In setup CCLK Data In hold Notes power-up, V must rise from 2 ...

Page 25

R Master Parallel Mode In Master Parallel mode, the lead FPGA directly addresses an industry-standard byte-wide EPROM and accepts eight data bits right before incrementing (or decrementing) the address outputs. The eight data bits are serialized in the lead FPGA, ...

Page 26

XC3000 Series Field Programmable Gate Arrays A0-A15 (output) D0-D7 RCLK (output) CCLK (output) DOUT (output) Description To address valid To data setup RCLK To data hold RCLK High RCLK Low Notes power-up, V must rise from 2.0 V ...

Page 27

R Peripheral Mode Peripheral mode uses the trailing edge of the logic AND condition of the CS0, CS1, CS2, and WS inputs to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a ...

Page 28

XC3000 Series Field Programmable Gate Arrays WRITE TO FPGA WS, CS0, CS1 CS2 T D0-D7 CCLK RDY/BUSY DOUT Description Effective Write time required (Assertion of CS0, CS1, CS2, WS) DIN Setup time required WRITE DIN Hold time required RDY/BUSY delay ...

Page 29

R Slave Serial Mode In Slave Serial mode, an external signal drives the CCLK input(s) of the FPGA(s). The serial configuration bitstream must be available at the DIN input of the lead FPGA a short set-up time before each rising ...

Page 30

XC3000 Series Field Programmable Gate Arrays DIN 1 T DCC CCLK DOUT (Output) Description To DOUT DIN setup CCLK DIN hold High time Low time (Note 1) Frequency Notes: 1. The max limit of CCLK Low time is caused by ...

Page 31

R Program Readback Switching Characteristics DONE/PROG (OUTPUT) RTRIG (M0) 4 CCLK( CCRD HI-Z M1 Input/ RDATA Output Description RTRIG RTRIG High RTRIG setup RDATA delay CCLK High time Low time Notes: 1. During Readback, CCLK frequency may not ...

Page 32

XC3000 Series Field Programmable Gate Arrays General XC3000 Series Switching Characteristics RESET M0/M1/ DONE/PROG INIT User State (Output) PWRDWN V (Valid) CC Description M0, M1, M2 setup time required RESET (2) M0, M1, M2 hold ...

Page 33

R Device Performance The XC3000 families of FPGAs can achieve very high per- formance. This is the result of • A sub-micron manufacturing process, developed and continuously being enhanced for the production of state-of-the-art CMOS SRAMs. • Careful optimization of ...

Page 34

XC3000 Series Field Programmable Gate Arrays 1.00 0.80 0.60 0.40 0.20 – 55 – 40 – 20 Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations 300 250 200 150 100 XC3100A-3 50 XC3000A--6 0 ...

Page 35

R Dynamic Power Consumption One CLB driving three local interconnects One global clock buffer and clock line One device output with load Power Consumption The Field Programmable Gate Array exhibits the low power consumption characteristic of CMOS ...

Page 36

XC3000 Series Field Programmable Gate Arrays Pin Descriptions Permanently Dedicated Pins V CC Two to eight (depending on package type) connections to the positive V supply voltage. All must be connected. GND Two to eight (depending on package type) connections ...

Page 37

R AND of several slave mode devices, a hold-off signal for a master mode device. After configuration this pin becomes a user-programmable I/O pin. BCLKIN This is a direct CMOS level input to the alternate clock buffer (Auxiliary Buffer) in ...

Page 38

XC3000 Series Field Programmable Gate Arrays Pin Functions During Configuration Configuration Mode <M2:M1:M0> SLAVE MASTER- MASTER- SERIAL SERIAL PERIPH HIGH <1:1:1> <0:0:0> <1:0:1> <1:1:0> POWR POWER POWER POWER DWN DWN DWN DWN (I) (I) (I) (I) M1 (HIGH) (I) M1 ...

Page 39

R XC3000A Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3000A Operating Conditions Symbol Supply ...

Page 40

XC3000 Series Field Programmable Gate Arrays XC3000A Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum ...

Page 41

R XC3000A CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...

Page 42

XC3000 Series Field Programmable Gate Arrays XC3000A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) ...

Page 43

R XC3000A IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...

Page 44

XC3000 Series Field Programmable Gate Arrays XC3000A IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O ...

Page 45

R XC3000L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3000L Operating Conditions Symbol V ...

Page 46

XC3000 Series Field Programmable Gate Arrays XC3000L Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum ...

Page 47

R XC3000L CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...

Page 48

XC3000 Series Field Programmable Gate Arrays XC3000L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) ...

Page 49

R XC3000L IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...

Page 50

XC3000 Series Field Programmable Gate Arrays XC3000L IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O ...

Page 51

R XC3100A Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3100A Operating Conditions Symbol Supply ...

Page 52

XC3000 Series Field Programmable Gate Arrays XC3100A Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum ...

Page 53

R XC3100A CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...

Page 54

XC3000 Series Field Programmable Gate Arrays XC3100A CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) ...

Page 55

... Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (Q) with latch transparent(XC3100A)Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time XC3120A, XC3130A XC3142A XC3164A XC3190A XC3195A Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew rate limited) Output (O) to Pad (fast) ...

Page 56

XC3000 Series Field Programmable Gate Arrays XC3100A IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O ...

Page 57

R XC3100L Switching Characteristics Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. XC3100L Operating Conditions Symbol V ...

Page 58

XC3000 Series Field Programmable Gate Arrays XC3100L Absolute Maximum Ratings Symbol V Supply voltage relative to GND CC V Input voltage with respect to GND IN V Voltage applied to 3-state output TS T Storage temperature (ambient) STG T Maximum ...

Page 59

R XC3100L CLB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...

Page 60

XC3000 Series Field Programmable Gate Arrays XC3100L CLB Switching Characteristics Guidelines (continued) CLB Output (X, Y) (Combinatorial) CLB Input (A,B,C,D,E) CLB Clock CLB Input (Direct In) CLB Input (Enable Clock) CLB Output (Flip-Flop) CLB Input (Reset Direct) CLB Output (Flip-Flop) ...

Page 61

R XC3100L IOB Switching Characteristics Guidelines Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing ...

Page 62

XC3000 Series Field Programmable Gate Arrays XC3100L IOB Switching Characteristics Guidelines (continued) I/O Block (I) I/O Pad Input I/O Clock (IK/OK) I/O Block (RI) RESET I/O Block (O) I/O Pad Output (Direct) I/O Pad Output (Registered) I/O Pad TS I/O ...

Page 63

R XC3000 Series Pin Assignments Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package types, with pin counts from 44 to 208. Each chip is offered in several package types ...

Page 64

XC3000 Series Field Programmable Gate Arrays XC3000 Series 64-Pin Plastic VQFP Pinouts XC3000A, XC3000L, and XC3100A families have identical pinouts Pin No. XC3030A 1 A0-WS-I/O 2 A1-CS2-I/O 3 A2-I/O 4 A3-I/O 5 A4-I/O 6 A14-I/O 7 A5-I/O 8 GND 9 ...

Page 65

R XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts 68 PLCC XC3020A, XC3030A, XC3030A XC3020A XC3042A 10 10 PWRDN 11 11 TCLKIN-I/O 12 — ...

Page 66

XC3000 Series Field Programmable Gate Arrays XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PLCC Pin Number XC3064A, XC3090A, XC3195A 12 PWRDN 13 TCLKIN-I ...

Page 67

R XC3000 Series 100-Pin QFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts Pin No. XC3020A TQFP XC3030A PQFP VQFP XC3042A 16 13 GND 17 14 A13-I A6-I A12-I A7-I ...

Page 68

XC3000 Series Field Programmable Gate Arrays XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA PGA Pin XC3042A Pin Number XC3064A Number C4 GND B13 A1 PWRDN C11 C3 I/O-TCLKIN A14 ...

Page 69

R XC3000 Series 144-Pin Plastic TQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts XC3042A Pin XC3064A Number XC3090A 1 PWRDN 2 I/O-TCLKIN 3 I/O* 4 I/O 5 I/O 6 I/O* 7 I/O 8 I/O 9 I/O* 10 ...

Page 70

XC3000 Series Field Programmable Gate Arrays XC3000 Series 160-Pin PQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PQFP Pin XC3064A, XC3090A, PQFP Pin Number XC3195A Number I/O ...

Page 71

R XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts PGA Pin PGA Pin XC3090A, XC3195A Number Number B2 PWRDN D13 D4 TCLKIN-I/O B14 B3 I/O C14 C4 I/O B15 B4 I/O ...

Page 72

XC3000 Series Field Programmable Gate Arrays XC3000 Series 176-Pin TQFP Pinouts XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts Pin Pin XC3090A Number Number 1 PWRDWN 45 2 TCLKIN I/O 49 ...

Page 73

R XC3000 Series 208-Pin PQFP Pinouts XC3000A, and XC3000L families have identical pinouts Pin Number XC3090A Pin Number 1 – GND 54 3 PWRDWN 55 4 TCLKIN ...

Page 74

XC3000 Series Field Programmable Gate Arrays XC3195A PQ208 Pinouts Pin Description PQ208 A9-I/O 206 A10-I/O 205 I/O 204 I/O 203 I/O 202 I/O 201 RDY/BUSY-RCLK-I/O A8-I/O 200 A11-I/O 199 I/O 198 I/O 197 I/O 196 I/O 194 A7-I/O 193 A12-I/O ...

Page 75

... CI XC3120A - - XC3130A - - XC3142A - XC3164A - XC3190A - XC3195A -2 -1 -09 November 9, 1998 (Version 3.1) XC3000 Series Field Programmable Gate Arrays 84 100 132 Plast. Cer. Plast. Plast. Plast. Plast. Cer. PLCC PGA PQFP TQFP VQFP PGA PGA PC84 PG84 PQ100 TQ100 VQ100 ...

Page 76

... VQ64 PC68 XC3142L XC3190L Notes Commercial, T Number of Available I/O Pins Max I/O XC3020A/XC3120A 64 XC3030A/XC3130A 80 XC3042A/3142A 96 XC2064A/XC3164A 120 XC3090A/XC3190A 144 XC3195A 176 Ordering Information Example: Device Type Speed Grade Revision History Date 11/98 Revised version number to 3.1, removed XC3100A-5 obsolete packages. 7-78 ...

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