XC3164A-4PC84C Xilinx Inc, XC3164A-4PC84C Datasheet - Page 9

• Manufacturer Part Number: XC3164A-4PC84C
• Description: FPGA XC3100A Family 4.5K Gates 224 Cells 227MHz CMOS Technology 5V 84-Pin PLCC
• Manufacturer: Xilinx Inc

Specifications of XC3164A-4PC84C

• Package: 84PLCC
• Family Name: XC3100A
• Device Logic Units: 224
• Device System Gates: 4500
• Number Of Registers: 688
• Maximum Internal Frequency: 227 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 70
• Ram Bits: 46064
• Re-programmability Support: Yes
• Dc: 97+

General Purpose Interconnect
General purpose interconnect, as shown in
sists of a grid of five horizontal and five vertical metal seg-
ments located between the rows and columns of logic and
IOBs. Each segment is the height or width of a logic block.
Switching matrices join the ends of these segments and
allow programmed interconnections between the metal grid
segments of adjoining rows and columns. The switches of
an unprogrammed device are all non-conducting. The con-
nections through the switch matrix may be established by
the automatic routing or by selecting the desired pairs of
matrix pins to be connected or disconnected. The legiti-
mate switching matrix combinations for each pin are indi-
cated in
Special buffers within the general interconnect areas pro-
vide periodic signal isolation and restoration for improved
performance of lengthy nets. The interconnect buffers are
available to propagate signals in either direction on a given
general interconnect segment. These bidirectional (bidi)
buffers are found adjacent to the switching matrices, above
November 9, 1998 (Version 3.1)
Figure 7: Counter.
The modulo-8 binary counter with parallel enable and
clock enable uses one combinatorial logic block of each
option.
Parallel Enable
Count Enable
Figure
Clock
D0
D1
D2
R
11.
Dual Function of 4 Variables
Function of 5 Variables
Function of 6 Variables
D
D
D
Figure
Q
Q
Q
FG
Mode
F
Mode
FGM
Mode
Terminal
Count
Q0
Q1
Q2
10, con-
X5383
XC3000 Series Field Programmable Gate Arrays
Direct Interconnect
Direct interconnect, shown in
efficient implementation of networks between adjacent
CLBs or I/O Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each CLB, the X output may be connected directly to
the B input of the CLB immediately to its right and to the C
input of the CLB to its left. The Y output can use direct inter-
connect to drive the D input of the block immediately above
and the A input of the block below. Direct interconnect
should be used to maximize the speed of high-performance
portions of logic. Where logic blocks are adjacent to IOBs,
direct connect is provided alternately to the IOB inputs (I)
and outputs (O) on all four edges of the die. The right edge
provides additional direct connects from CLB outputs to
adjacent IOBs. Direct interconnections of IOBs with CLBs
are shown in
and to the right. The other PIPs adjacent to the matrices
are accessed to or from Longlines. The development sys-
tem automatically defines the buffer direction based on the
location of the interconnection network source. The delay
calculator of the development system automatically calcu-
lates and displays the block, interconnect and buffer delays
for any paths selected. Generation of the simulation netlist
with a worst-case delay model is provided.
Figure 8: A Design Editor view of routing resources
used to form a typical interconnection network from
CLB GA.
Figure
13.
Figure
12, provides the most
7-11
7