XC3164A-4PC84C Xilinx Inc, XC3164A-4PC84C Datasheet - Page 49

• Manufacturer Part Number: XC3164A-4PC84C
• Description: FPGA XC3100A Family 4.5K Gates 224 Cells 227MHz CMOS Technology 5V 84-Pin PLCC
• Manufacturer: Xilinx Inc

Specifications of XC3164A-4PC84C

• Package: 84PLCC
• Family Name: XC3100A
• Device Logic Units: 224
• Device System Gates: 4500
• Number Of Registers: 688
• Maximum Internal Frequency: 227 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 70
• Ram Bits: 46064
• Re-programmability Support: Yes
• Dc: 97+

XC3000L IOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the timing calculator and used
in the simulator.
Notes:
November 9, 1998 (Version 3.1)
Propagation Delays (Input)
Set-up Time (Input)
Propagation Delays (Output)
Set-up and Hold Times (Output)
Clock
Global Reset Delays (based on XC3042L)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
Pad to Clock (IK) set-up time
Clock (OK) to Pad
same
Output (O) to Pad
same
3-state to Pad begin hi-Z
same
3-state to Pad active and valid
same
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
Clock High time
Clock Low time
Max. flip-flop toggle rate
RESET Pad to Registered In
RESET Pad to output pad
1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
4. T
rise/fall times are approximately four times longer.
pull-up resistor or alternatively configured as a driven output or driven from an external source.
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
PID
R
, T
PTG
, and T
PICK
are 3 ns higher for XTL2 when the pin is configured as a user input.
Description
(fast)
(slew rate limited)
(fast)
(slew-rate limited)
(fast)
(slew-rate limited)
(fast)
(slew -rate limited)
(Q)
(slew-rate limited)
(fast)
XC3000 Series Field Programmable Gate Arrays
10
10
11
12
13
15
15
3
4
1
7
7
9
9
8
8
5
6
Speed Grade
Symbol
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
F
T
T
T
T
OKPO
OKPO
TSON
TSON
TSHZ
TSHZ
PICK
OOK
OKO
RPO
RPO
PTG
OPF
OPS
IKRI
CLK
PID
IOH
RRI
IOL
22.0
12.0
80.0
Min
5.0
5.0
0
-8
Max
24.0
12.0
28.0
25.0
12.0
28.0
16.0
32.0
25.0
35.0
51.0
5.0
6.0
9.0
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7-51
7