XC3164A-4PC84C Xilinx Inc, XC3164A-4PC84C Datasheet - Page 34

• Manufacturer Part Number: XC3164A-4PC84C
• Description: FPGA XC3100A Family 4.5K Gates 224 Cells 227MHz CMOS Technology 5V 84-Pin PLCC
• Manufacturer: Xilinx Inc

Specifications of XC3164A-4PC84C

• Package: 84PLCC
• Family Name: XC3100A
• Device Logic Units: 224
• Device System Gates: 4500
• Number Of Registers: 688
• Maximum Internal Frequency: 227 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 70
• Ram Bits: 46064
• Re-programmability Support: Yes
• Dc: 97+

XC3000 Series Field Programmable Gate Arrays
Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations
Figure 33: Clock Rate as a Function of Logic
Complexity (Number of Combinational Levels between
Flip-Flops)
7-36
Gate Levels:
CLB Levels:
300
250
200
150
100
50
0
XC3100A-3
XC3000A--6
1.00
0.80
0.60
0.40
0.20
4 CLBs
(4-16)
– 55
3 CLBs
(3-12)
– 40
2 CLBs
(2-8)
– 20
1 CLB
(1-4)
0
TYPICAL COMMERCIAL
TYPICAL MILITARY
Toggle
X7065
Rate
(+ 5.0 V, 25 C)
TEMPERATURE ( C)
25
Power
Power Distribution
Power for the FPGA is distributed through a grid to achieve
high noise immunity and isolation between logic and I/O.
Inside the FPGA, a dedicated V
rounding the logic array provides power to the I/O drivers.
An independent matrix of V
interior logic of the device. This power distribution grid pro-
vides a stable supply and ground for all internal logic, pro-
viding the external package power pins are all connected
and appropriately decoupled. Typically a 0.1- F capacitor
connected near the V
quate decoupling.
Output buffers capable of driving the specified 4- or 8-mA
loads under worst-case conditions may be capable of driv-
ing as much as 25 to 30 times that current in a best case.
Noise can be reduced by minimizing external load capaci-
tance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the ground pads. The I/O Block
output buffers have a slew-limited mode which should be
used where output rise and fall times are not speed critical.
Slew-limited outputs maintain their dc drive capability, but
generate less external reflections and internal noise.
40
70
SPECIFIED WORST-CASE VALUES
CC
80
and ground pins will provide ade-
November 9, 1998 (Version 3.1)
CC
and groundlines supplies the
100
CC
and ground ring sur-
125
X6094
R