XC3164A-4PC84C Xilinx Inc, XC3164A-4PC84C Datasheet - Page 74

• Manufacturer Part Number: XC3164A-4PC84C
• Description: FPGA XC3100A Family 4.5K Gates 224 Cells 227MHz CMOS Technology 5V 84-Pin PLCC
• Manufacturer: Xilinx Inc

Specifications of XC3164A-4PC84C

• Package: 84PLCC
• Family Name: XC3100A
• Device Logic Units: 224
• Device System Gates: 4500
• Number Of Registers: 688
• Maximum Internal Frequency: 227 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 70
• Ram Bits: 46064
• Re-programmability Support: Yes
• Dc: 97+

XC3000 Series Field Programmable Gate Arrays
XC3195A PQ208 Pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed outputs are
default slew-rate limited.
In the PQ208 package, pins 15, 16, 64, 65, 90, 91, 142, 143, 170 and 195 are not connected.
* In PQ208, XC3090A and XC3195A have different pinouts.
7-76
Pin Description
A1-CS2-I/O
A0-WS-I/O
DOUT-I/O
A10-I/O
A11-I/O
A12-I/O
A13-I/O
A14-I/O
A15-I/O
A9-I/O
A8-I/O
A7-I/O
A6-I/O
A5-I/O
A4-I/O
A3-I/O
A2-I/O
CCLK
GND
GND
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PQ208
206
205
204
203
202
201
200
199
198
197
196
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
RDY/BUSY-RCLK-I/O
XTLX1(OUT)BCLKN-I/O
Pin Description
XTL2(IN)-I/O
D0-DIN-I/O
CS1-I/O
CS0-I/O
RESET
D1-I/O
D2-I/O
D3-I/O
D4-I/O
D5-I/O
D6-I/O
D7-I/O
GND
VCC
VCC
GND
D/P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PQ208
154
153
152
151
150
149
148
147
146
145
144
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
Pin Description
M1/RDATA
M0-RTIG
HDC-I/O
LDC-I/O
M2-I/O
GND
GND
VCC
VCC
INIT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PQ208
102
101
100
99
98
97
96
95
94
93
92
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
November 9, 1998 (Version 3.1)
Pin Description
TCLKIN-I/O
PWRDN
GND
VCC
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PQ208
208
207
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
14
13
12
11
10
9
8
7
6
5
4
3
1
2
R