XC3164A-4PC84C Xilinx Inc, XC3164A-4PC84C Datasheet - Page 38

• Manufacturer Part Number: XC3164A-4PC84C
• Description: FPGA XC3100A Family 4.5K Gates 224 Cells 227MHz CMOS Technology 5V 84-Pin PLCC
• Manufacturer: Xilinx Inc

Specifications of XC3164A-4PC84C

• Package: 84PLCC
• Family Name: XC3100A
• Device Logic Units: 224
• Device System Gates: 4500
• Number Of Registers: 688
• Maximum Internal Frequency: 227 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 70
• Ram Bits: 46064
• Re-programmability Support: Yes
• Dc: 97+

XC3000 Series Field Programmable Gate Arrays
Pin Functions During Configuration
7-40
M1 (HIGH) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
RESET (I)
CCLK (I)
SERIAL
<1:1:1>
SLAVE
POWR
DONE
DIN (I)
Notes:
Note
DOUT
DWN
INIT*
GND
****
***
(I)
(I)
**
*
:
Generic I/O pins are not shown.
For a detailed description of the configuration modes, see
For pinout details, see
Represents a weak pull-up before and during configuration.
INIT is an open drain output during configuration.
Represents an input.
Pin assignment for the XC3064A/XC3090A and XC3195A differ from those shown.
Peripheral mode and master parallel mode are not supported in the PC44 package.
Pin assignments for the XC3195A PQ208 differ from those shown.
Pin assignments of PGA Footprint PLCC sockets and PGA packages are not identical.
The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a weak pull-up resistor.
M1 (LOW) (I)
M0 (LOW) (I)
M2 (LOW) (I)
HDC (HIGH)
LDC (LOW)
MASTER-
RESET (I)
CCLK (O)
POWER
SERIAL
<0:0:0>
DONE
DIN (I)
DOUT
DWN
INIT*
GND
Configuration Mode <M2:M1:M0>
(I)
M0 (HIGH) (I)
M2 (HIGH) (I)
M1 (LOW) (I)
HDC (HIGH)
LDC (LOW)
RDY/BUSY
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
RESET (I)
CCLK (O)
PERIPH
POWER
<1:0:1>
CS0 (I)
CS1 (I)
CS2 (I)
DONE
DOUT
WS (I)
DWN
INIT*
GND
(I)
page 65
M1 (HIGH) (I)
M2 (HIGH) (I) M2 (HIGH) (I)
M0 (LOW) (I)
HDC (HIGH)
LDC (LOW)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
MASTER-
RESET (I)
CCLK (O)
POWER
<1:1:0>
DONE
DOUT
RCLK
HIGH
DWN
INIT*
GND
A15
A14
A13
A12
A11
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
(I)
through
page
M1 (LOW) (I)
M0 (LOW) (I)
HDC (HIGH)
LDC (LOW)
MASTER-
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
RESET (I)
CCLK (O)
POWER
<1:0:0>
DONE
DOUT
RCLK
LOW
DWN
INIT*
GND
A15
A14
A13
A12
A11
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
(I)
76.
PLCC
***
44
16
17
18
19
20
22
23
26
27
28
30
38
39
40
X
7
page 25
VQFP
64
17
31
32
33
34
36
40
41
47
48
49
50
51
52
53
54
55
57
58
59
60
61
62
63
64
10
11
12
13
14
15
16
X
1
2
3
4
5
6
7
9
PLCC
through
68
10
25
26
27
28
30
34
35
43
44
45
46
47
48
49
50
51
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
X
X
2
3
4
5
6
7
8
9
PLCC
X**
X**
X**
84
12
31
32
33
34
36
42
43
53
54
55
56
57
58
60
61
62
65
66
67
70
71
72
73
74
75
76
77
78
81
82
83
84
10
11
**
X
X
X
2
3
4
5
8
9
page
PGA
H10
G10
G11
D10
C11
C10
L11
K10
J10
K11
J11
F10
F11
E11
E10
B11
A11
B10
A10
B2
K2
K3
K6
B9
A9
B6
B7
A7
C7
A6
A5
B5
C5
A3
A2
B3
A1
84
J2
L1
L3
J6
X
X
X
34.
PQFP
100
100
29
52
54
56
57
59
65
66
76
78
80
81
82
83
87
88
89
92
93
94
98
99
12
13
14
15
17
18
19
20
23
24
25
26
1
X
X
X
2
5
6
8
9
VQFP
TQFP
100
26
49
51
53
54
56
62
63
73
75
77
78
79
80
84
85
86
89
90
91
95
96
97
98
99
10
11
12
14
15
16
17
20
21
22
26
X
X
2
3
5
6
9
PGA
B13
A14
C13
B14
D14
G14
H12
M13
N13
M12
P13
N11
132
P14
M9
M6
M5
M3
M2
A1
N9
N8
N7
P6
N4
N2
P1
N1
K1
H1
H2
G2
G1
E1
D1
D2
B1
C2
L2
L1
J2
F2
X
X
TQFP
144
102
103
106
107
108
111
112
115
116
119
120
123
124
128
129
133
134
137
138
141
142
36
38
40
41
45
53
55
69
71
73
74
75
78
84
85
88
92
93
96
1
X
X
X
November 9, 1998 (Version 3.1)
PQFP
160
159
102
103
106
114
115
119
120
121
124
125
128
129
132
133
136
137
141
142
147
148
151
152
155
156
40
42
44
45
49
59
61
76
78
80
81
82
86
92
93
96
X
X
PGA
B14
B15
C15
E14
D16
H15
P15
R15
R14
N13
P12
R10
175
J14
T14
T11
M3
M1
B2
R9
P8
R8
R7
R5
P5
R3
N4
R2
P2
P1
N1
K2
K1
H2
H1
F2
E1
D1
C1
E3
C2
L2
X
X
TQFP
176
102
103
108
112
113
118
124
125
130
131
132
135
136
140
141
146
147
150
151
156
157
164
165
169
170
173
174
89
96
45
47
49
50
54
65
67
85
87
90
91
1
X
PQFP
****
208
100
102
107
109
110
115
122
123
128
132
133
138
145
146
151
152
153
161
162
165
166
172
173
178
179
184
185
192
193
199
200
203
204
48
50
56
57
61
77
79
3
X
X
PROGRAM (I)
XC3x20A etc.
XC3x30A etc.
XC3x42A etc.
XC3x64A etc.
XC3x90A etc.
XTL2 OR I/O
XTL1 OR I/O
RESET (I)
RTRIG (I)
All Others
Function
XC3195A
CCLK (I)
POWER
RDATA
DWN
User
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
(1)
5
R