GS84036AT-166 GSI TECHNOLOGY, GS84036AT-166 Datasheet - Page 11

• Manufacturer Part Number: GS84036AT-166
• Description: SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 8.5ns/3.5ns 100-Pin TQFP Tray
• Manufacturer: GSI TECHNOLOGY

Specifications of GS84036AT-166

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 4 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 4
• Number Of Words: 128K

Mode Pin Functions
Note:
There are pull-up devices on LBO and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.19a 2/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
1st address
2nd address
3rd address
4th address
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
00
11
Name
10
11
00
01
LBO
Pin
ZZ
FT
00
01
10
11
H or NC
H or NC
L or NC
State
H
L
L
11/31
Standby, I
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst
1st address
2nd address
3rd address
4th address
Flow Through
Linear Burst
Function
Pipeline
Active
DD
= I
SB
GS84018/32/36AT/B-180/166/150/100
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
00
11
10
10
00
01
11
© 1999, GSI Technology
11
10
01
00