GS84036AT-166 GSI TECHNOLOGY, GS84036AT-166 Datasheet - Page 15

• Manufacturer Part Number: GS84036AT-166
• Description: SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 8.5ns/3.5ns 100-Pin TQFP Tray
• Manufacturer: GSI TECHNOLOGY

Specifications of GS84036AT-166

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 4 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 36 Bit
• Number Of Ports: 4
• Number Of Words: 128K

Notes:
1.
2.
3.
Rev: 1.19a 2/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet
Data Input Set Up Time.
X
X
CW
First Write
Burst Write
W
Simplified State Diagram with G
W
CW
15/31
W
CR
R
CR
R
Deselect
X
CW
W
CW
W
R
GS84018/32/36AT/B-180/166/150/100
CR
First Read
Burst Read
R
R
CR
X
X
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