CN8237EBGB Mindspeed Technologies, CN8237EBGB Datasheet - Page 131

• Manufacturer Part Number: CN8237EBGB
• Description: ATM SAR 622Mbps 3.3V ABR/CBR/GFR/UBR/VBR 456-Pin BGA
• Manufacturer: Mindspeed Technologies

Specifications of CN8237EBGB

• Package: 456BGA
• Traffic Class: ABR|CBR|GFR|UBR|VBR
• Utopia Type: Level 1|Level 2
• Host Interface: PCI
• Maximum Data Rate: 622 Mbps
• Typical Operating Supply Voltage: 3.3 V
• Minimum Operating Supply Voltage: 3.135 V

CN8237
ATM OC-12 ServiceSAR Plus with xBR Traffic Management
5.4.10 Firewall Functions
28237-DSH-001-C
5.4.10.2 Operation
5.4.10.1 Setup
Implementation of multiple free buffer queues and EPD performs a firewalling
functionality on a group basis.
The firewall mechanism allows the user to allocate buffer credits on a per-channel
basis.
NOTE:
Set RSM_FQCTRL(FBQ0_RTN) to a logic high. This sets free buffer queue
block 0 to contain queues with 4-word entries. This is used to support per-VCC
firewall credit update.
(FWALL_EN), to globally enable firewall processing on a per-channel basis.
firewall processing:
the entry where credit is initially returned. Typically, this is the first entry after the
initial buffers placed on the queue. Write the FWD_VLD bit in all free buffer
queue entries to a logic low.
Whenever a buffer is taken off free buffer queues 0–15 during reassembly on a
channel enabled for firewall processing, the RSM coprocessor decrements the
RX_COUNTER[15:0] in the RSM VCC table entry for that channel. This allows
COM buffers to be placed on queues 16–31 without being firewalled.
RSM coprocessor declares a firewall condition. If the firewall condition occurs
on a BOM or SSM, the CN8237 writes a status queue entry with the FW bit set
and a NULL in the BD_PNTR field.
initiates EPD and writes a status queue entry with the FW and EPD bits set. It
then discards cells on that channel until the channel has recovered from the
firewall condition.
AAL5_DSC_CNT counter to be incremented. Recovery occurs only on a BOM
or SSM cell when the credit is rechecked.
The user can also set up per-VCC firewalling on a channel-by-channel basis.
Set the global firewall control bit to a logic high in register RSM_CTRL0, field
Set the following fields of the VCC table entry for the channel being set up for
• The FW_EN bit set to a logic high enables firewall processing on that
• Set RX_COUNTER[15:0] to assign the initial buffer credit for the channel.
Initialize the FORWARD fields in the free buffer queue base tables to point to
If the RX_COUNTER[15:0] for a channel is 0 when a buffer is required, the
If the firewall condition occurs on a COM or EOM, the RSM coprocessor
All AAL5 PDUs discarded under the firewall condition cause the
When firewalling is enabled in the RSM coprocessor and an FBQ empty
(underflow) condition is encountered, the RX_COUNTER field in the
VCC table(s) still decrements each time the VCC receives a BOM cell.
The RX_COUNTER should not be decremented when the FBQ is empty.
There is no workaround for this problem. The user “must” avoid FBQ
empty conditions when firewalling is enabled.
channel.
Mindspeed Technologies
™
5.0 Reassembly Coprocessor
5.4 Buffer Management
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