LPC1754FBD80,518 NXP Semiconductors, LPC1754FBD80,518 Datasheet - Page 34

• Manufacturer Part Number: LPC1754FBD80,518
• Description: IC MCU 32BIT 128KB FLASH 80LQFP
• Manufacturer: NXP Semiconductors
• Series: LPC17xxr

Specifications of LPC1754FBD80,518

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 100MHz
• Connectivity: CAN, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 6x12b, D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Package: 80LQFP
• Device Core: ARM Cortex M3
• Family Name: LPC1700
• Maximum Speed: 100 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 52
• Interface Type: CAN/I2C/SPI/UART/USB
• On-chip Adc: 6-chx12-bit
• Number Of Timers: 4
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC1759_58_56_54_52_51
Product data sheet
7.30.1 Reset
7.30 System control
Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt
trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains
a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see
description in
until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks
have passed, and the flash controller has completed its initialization. Once reset is
de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD
threshold, the RSTOUT pin goes HIGH.
When the internal Reset is removed, the processor begins executing at address 0, which
is initially the Reset vector mapped from the boot block. At that point, all of the processor
and peripheral registers have been initialized to predetermined values.
Fig 5.
Power distribution
V
DD(REG)(3V3)
Section
All information provided in this document is subject to legal disclaimers.
V
DD(3V3)
VREFP
VREFN
RTCX1
RTCX2
VBAT
V
V
V
DDA
SSA
SS
7.29.4). The wake-up timer ensures that reset remains asserted
Rev. 7 — 29 March 2011
LPC17xx
RTC POWER DOMAIN
ADC POWER DOMAIN
MAIN POWER DOMAIN
OSCILLATOR
SELECTOR
to I/O pads
POWER
32 kHz
LPC1759/58/56/54/52/51
REGULATOR
32-bit ARM Cortex-M3 microcontroller
ULTRA LOW-POWER
REGULATOR
BACKUP REGISTERS
DAC
ADC
REAL-TIME CLOCK
to core
to memories,
peripherals,
oscillators,
PLLs
002aad978
© NXP B.V. 2011. All rights reserved.
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