P89LPC9321FN NXP Semiconductors, P89LPC9321FN Datasheet - Page 19
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P89LPC9321FN
Manufacturer Part Number
P89LPC9321FN
Description
MCU 8-Bit 89LP 80C51 CISC 8KB Flash 2.5V/3.3V 28-Pin PDIP Tube
Manufacturer
NXP Semiconductors
Datasheet
1.P89LPC9321FN.pdf
(70 pages)
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Table 4.
* indicates SFRs that are bit addressable.
[1]
[2]
[3]
[4]
[5]
[6]
Name
WDL
WFEED1
WFEED2
All ports are in input only (high-impedance) state after power-up.
BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
The RSTSRC register reflects the cause of the P89LPC9321 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on
reset value is x011 0000.
After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
The only reset sources that affect these SFRs are power-on reset and watchdog reset.
Special function registers
Description
Watchdog load
Watchdog
feed 1
Watchdog
feed 2
SFR
addr.
C1H
C2H
C3H
Bit functions and addresses
…continued
MSB
LSB
Reset value
Hex
FF
Binary
1111 1111
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