P89LPC9321FN NXP Semiconductors, P89LPC9321FN Datasheet - Page 37

• Manufacturer Part Number: P89LPC9321FN
• Description: MCU 8-Bit 89LP 80C51 CISC 8KB Flash 2.5V/3.3V 28-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC9321_1
Product data sheet
7.23.10 The 9
7.23.7 Break detect
7.23.8 Double buffering
7.23.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
7.24 I
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the device
and force the device into ISP mode.
The UART has a transmit double buffer that allows buffering of the next character to be
written to SnBUF while the first character is being transmitted. Double buffering allows
transmission of a string of characters with only one stop bit between any two characters,
as long as the next character is written between the start bit and the stop bit of the
previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT.7 = 0), the UART is
compatible with the conventional 80C51 UART. If enabled, the UART allows writing to
SBUF while the previous data is being shifted out. Double buffering is only allowed in
Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled
(DBMOD = 0).
Unlike the conventional UART, in double buffering mode, the TI interrupt is generated
when the double buffer is ready to receive new data.
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TI interrupt.
If double buffering is enabled, TB must be updated before SBUF is written, as TB8 will be
double-buffered together with SBUF data.
The I
connected to the bus, and it has the following features:
A typical I
byte-oriented I
2
•
•
•
•
•
•
C-bus serial interface
Bidirectional data transfer between masters and slaves
Multi master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
The I
2
C-bus uses two wires (SDA and SCL) to transfer information between devices
th
bit (bit 8) in double buffering (modes 1, 2 and 3)
2
2
C-bus may be used for test and diagnostic purposes.
C-bus configuration is shown in
2
C-bus interface that supports data transfers up to 400 kHz.
Rev. 01 — 9 December 2008
8-bit microcontroller with accelerated two-clock 80C51 core
Figure
13. The P89LPC9321 device provides a
P89LPC9321
© NXP B.V. 2008. All rights reserved.
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