P89LPC9321FN NXP Semiconductors, P89LPC9321FN Datasheet - Page 46

• Manufacturer Part Number: P89LPC9321FN
• Description: MCU 8-Bit 89LP 80C51 CISC 8KB Flash 2.5V/3.3V 28-Pin PDIP Tube
• Manufacturer: NXP Semiconductors

NXP Semiconductors
P89LPC9321_1
Product data sheet
7.30.1 General description
7.30.2 Features
7.30.3 Flash organization
7.30 Flash program memory
After the operation finishes, the hardware will set the EEIF bit, which if enabled will
generate an interrupt. The flag is cleared by software.
Remark: When voltage supply is lower than 2.4 V, the BOD FLASH is tripped and Data
EEPROM program or erase is blocked. EWERR1 and EWERR0 bits are used to indicate
the write error for BOD EEPROM. Both can be cleared by power on reset, watchdog reset
or software write.
The P89LPC9321 flash memory provides in-circuit electrical erasure and programming.
The flash can be erased, read, and written as bytes. The Sector and Page Erase functions
can erase any flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase
the entire program memory. ICP using standard commercial programmers is available. In
addition, IAP and byte-erase allows code memory to be used for non-volatile data storage.
On-chip erase and write timing generation contribute to a user-friendly programming
interface. The P89LPC9321 flash reliably stores memory contents even after
100,000 erase and program cycles. The cell is designed to optimize the erase and
programming mechanisms. The P89LPC9321 uses V
the Program/Erase algorithms. When voltage supply is lower than 2.4 V, the BOD FLASH
is tripped and flash erase/program is blocked.
The program memory consists of eight 1 kB sectors on the P89LPC9321 devices. Each
sector can be further divided into 64-byte pages. In addition to sector erase, page erase,
and byte erase, a 64-byte page register is included which allows from 1 to 64 bytes of a
given page to be programmed at the same time, substantially reducing overall
programming time.
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Programming and erase over the full operating voltage range.
Byte erase allows code memory to be used for data storage.
Read/Programming/Erase using ISP/IAP/ICP.
Internal fixed boot ROM, containing low-level IAP routines available to user code.
Default loader providing ISP via the serial port, located in upper end of user program
memory.
Boot vector allows user-provided flash loader code to reside anywhere in the flash
memory space, providing flexibility to the user.
Any flash program/erase operation in 2 ms.
Programming with industry-standard commercial programmers.
Programmable security for the code in the flash for each sector.
100,000 typical erase/program cycles for each byte.
10 year minimum data retention.
Rev. 01 — 9 December 2008
8-bit microcontroller with accelerated two-clock 80C51 core
DD
as the supply voltage to perform
P89LPC9321
© NXP B.V. 2008. All rights reserved.
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