STM32F405RGT6 STMicroelectronics, STM32F405RGT6 Datasheet - Page 108

• Manufacturer Part Number: STM32F405RGT6
• Description: Microcontrollers (MCU) ARM M4 1024 FLASH 168 Mhz 192kB SRAM
• Manufacturer: STMicroelectronics

Specifications of STM32F405RGT6

• Core: ARM Cortex M4
• Processor Series: STM32F4
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 168 MHz
• Program Memory Size: 1024 KB
• Data Ram Size: 192 KB
• On-chip Adc: Yes
• Number Of Programmable I/os: 51
• Number Of Timers: 10
• Operating Supply Voltage: 1.7 V to 3.6 V
• Package / Case: LQFP-64
• Mounting Style: SMD/SMT
• A/d Bit Size: 12 bit
• A/d Channels Available: 16
• Interface Type: CAN, I2C, I2S, SPI, UART
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Details

Electrical characteristics
108/167
I
Unless otherwise specified, the parameters given in
are derived from tests performed under the ambient temperature, f
supply voltage conditions summarized in
Refer to
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I
Table 52.
1. Remapped SPI1 characteristics to be determined.
2. TBD stands for “to be defined”.
3. Based on characterization, not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
2
DuCy(SCK)
t
t
t
dis(SO)
t
S - SPI interface characteristics
t
t
t
w(SCLH)
v(SO)
t
w(SCLL)
a(SO)
v(MO)
1/t
su(NSS)
t
Symbol
t
h(NSS)
t
t
t
su(MI)
t
h(MO)
the data.
the data in Hi-Z
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCL)
f
f(SCL)
c(SCK)
SCK
(3)(4)
(3)(1)
(3)(1)
(3)
(3)(5)
(3)
(3)
(3)
(3)
(3)
(3)
Section 5.3.16: I/O port characteristics
(3)
(3)
(3)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock
duty cycle
NSS setup time
NSS hold time
SCK high and low time Master mode, f
Data input setup time
Data input hold time
Data output access
time
Data output disable
time
Data output valid time Slave mode (after enable edge)
Data output valid time Master mode (after enable edge)
Data output hold time
Parameter
Doc ID 022152 Rev 2
(1)(2)
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Table
Conditions
11.
for more details on the input/output alternate
PCLK
PCLK
= 20 MHz
Table 52
= TBD MHz
STM32F405xx, STM32F407xx
for SPI or in
PCLKx
4t
2t
TBD
Min
PCLK
PCLK
30
15
5
5
5
4
2
2
-
-
-
-
-
0
frequency and V
Table 53
3 t
TBD
Max
37.5
37.5
70
10
25
2
PCLK
-
-
-
8
-
-
-
-
5
-
S).
for I
MHz
Unit
ns
ns
%
2
S
DD