RC28F128P33BF60A Micron Technology Inc, RC28F128P33BF60A Datasheet - Page 20

• Manufacturer Part Number: RC28F128P33BF60A
• Manufacturer: Micron Technology Inc

Specifications of RC28F128P33BF60A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

7.0
7.1
7.2
Datasheet
20
Read Operation
The device can be in any of four read states: Read Array, Read Identifier, Read Status
or Read Query. Upon power-up, or after a reset, the device defaults to Read Array
mode. To change the read state, the appropriate read command must be written to the
device (see
sections describe read-mode operations in detail.
The device supports two read modes: asynchronous page mode and synchronous burst
mode. Asynchronous page mode is the default read mode after device power-up or a
reset. The RCR must be configured to enable synchronous burst reads of the flash
memory array (see
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read
mode and the device is set to Read Array mode. However, to perform array reads after
any other device operation (e.g. write operation), the Read Array command must be
issued in order to read from the flash memory array.
To perform an asynchronous page-mode read, an address is driven onto the address
bus, and CE# and ADV# are asserted. WE# and RST# must already have been
deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven
high to latch the address, or it must be held low throughout the read cycle. CLK is not
used for asynchronous page-mode reads, and is ignored. If only asynchronous reads
are to be performed, CLK should be tied to a valid V
floated and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an
initial access time t
In asynchronous page mode, eight data words are “sensed” simultaneously from the
flash memory array and loaded into an internal page buffer. The buffer word
corresponding to the initial address on the Address bus is driven onto DQ[15:0] after
the initial access delay. The lowest four address bits determine which word of the
16-word page is output from the data buffer at any given time.
Synchronous Burst-Mode Read
To perform a synchronous burst-read, an initial address is driven onto the address bus,
and CE# and ADV# are asserted. WE# and RST# must already have been deasserted.
ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can
remain asserted throughout the burst access, in which case the address is latched on
the next valid CLK edge while ADV# is asserted.
During synchronous array and non-array read modes, the first word is output from the
data buffer on the next valid CLK edge after the initial access latency delay (see
11.1.2, “Latency Count (RCR[13:11])” on page
CLK edges following a minimum delay. However, for a synchronous non-array read, the
same word of data will be output on successive clock edges until the burst length
requirements are satisfied. Refer to the following waveforms for more detailed
information:
•
•
•
Figure 20, “Synchronous Single-Word Array or Non-array Read Timing” on page 52
Figure 21, “Continuous Burst Read, showing an Output Delay Timing” on page 53
Figure 22, “Synchronous Burst-Mode Four-Word Read Timing” on page 53
Section 6.2, “Device Command Bus Cycles” on page
AVQV
Section 11.1, “Read Configuration Register” on page
delay. (see
Section 15.0, “AC Characteristics” on page
34). Subsequent data is output on valid
IH
or V
IL
level, WAIT signal can be
18). The following
Order Number: 208034-04
33).
P33-65nm
48).
Section
Jul 2011