RC28F128P33BF60A Micron Technology Inc, RC28F128P33BF60A Datasheet - Page 34

• Manufacturer Part Number: RC28F128P33BF60A
• Manufacturer: Micron Technology Inc

Specifications of RC28F128P33BF60A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Table 12: Read Configuration Register Description (Sheet 2 of 2)
11.1.1
11.1.2
Datasheet
34
5:4
3
2:0
Reserved (R)
Burst Wrap (BW)
Burst Length (BL[2:0])
Read Mode (RCR.15)
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
Latency Count (RCR[13:11])
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is driven onto DQ[15:0]. The input clock frequency is used to
determine this value and
settings of LC. The maximum Latency Count for P33 would be Code 4 based on the Max
clock frequency specification of 52 MHz, and there will be zero WAIT States when
bursting within the word line. Please also refer to
(EOWL) Considerations” on page 36
Refer to
Table 13, “LC and Frequency Support” on page 35
Set to 0. This bit cannot be altered by customer.
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
(Other bit settings are reserved)
Figure 8
shows the data output latency for the different
for more information on EOWL.
Section 11.1.3, “End of Word Line
for Latency Code Settings.
Order Number: 208034-04
P33-65nm
Jul 2011