IDT82P2821BHG IDT, Integrated Device Technology Inc, IDT82P2821BHG Datasheet - Page 90

• Manufacturer Part Number: IDT82P2821BHG
• Description: IC LINE INTERFACE UNIT 640-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2821BHG

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1703; 82P2821BHG

TCF1 - Transmit Configuration Register 1
Address: 005H, 045H, 085H, 0C5H, 105H, 145H, 185H, 1C5H, (CH1~CH8)
Type: Read / Write
Default Value: 01H
Programming Information
IDT82P2821
TMF_DEF2
7 - 5
1 - 0
Bit
4
3
2
205H, 245H, 285H, 2C5H, 305H, 345H, 385H, 3C5H, (CH9~CH16)
405H, 445H, 485H, 4C5H, 505H, (CH17~CH21)
7C5H (CH0)
7
TMF_DEF[2:0] These bits are valid only in Transmit Dual Rail RZ Format mode and Transmit Single Rail NRZ Format mode. They determine the
T_MD[1:0]
T_CODE
TCK_ES
TD_INV
Name
TMF_DEF1
6
indication on the TMFn pin.
000: PRBS/ARB indication when the PRBS/ARB detection is switched to the transmit path. Or reserved when the PRBS/ARB
detection is switched to the receive path. (default)
001: SAIS indication.
010: TOC indication.
011: TLOS indication.
100: SEXZ indication.
101: SBPV indication in Transmit Dual Rail RZ Format mode. Reserved in Transmit Single Rail NRZ Format mode.
110: SEXZ + SBPV indication in Transmit Dual Rail RZ Format mode. Reserved in Transmit Single Rail NRZ Format mode.
111: SLOS indication in Transmit Dual Rail RZ Format mode. Reserved in Transmit Single Rail NRZ Format mode.
This bit selects the active edge of the TCLKn pin.
0: Falling edge. (default)
1: Rising edge.
This bit determines the active level on the TDn, TDPn and TDNn pins.
0: Active high. (default)
1: Active low.
This bit selects the line code rule for the transmit path.
0: B8ZS (in T1/J1 mode) / HDB3 (in E1 mode). (default)
1: AMI.
These bits determines the transmit system interface.
00: Transmit Single Rail NRZ Format system interface. The data is input on TDn in NRZ format and a 1.544 MHz (in T1/J1 mode)
or 2.048 MHz (in E1 mode) clock is input on TCLKn.
01: Transmit Dual Rail NRZ Format system interface. The data is input on TDPn and TDNn in NRZ format and a 1.544 MHz (in
T1/J1 mode) or 2.048 MHz (in E1 mode) clock is input on TCLKn. (default)
10: Transmit Dual Rail RZ Format system interface. The data is input on TDPn and TDNn in RZ format.
11: Reserved.
TMF_DEF0
5
TCK_ES
4
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
90
TD_INV
3
Description
T_CODE
2
T_MD1
1
February 6, 2009
T_MD0
0