IDT82P2821BHG IDT, Integrated Device Technology Inc, IDT82P2821BHG Datasheet - Page 97
IDT82P2821BHG
Manufacturer Part Number
IDT82P2821BHG
Description
IC LINE INTERFACE UNIT 640-PBGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT82P2821BHG.pdf
(151 pages)
Specifications of IDT82P2821BHG
Function
Line Interface Unit (LIU)
Interface
E1, J1, T1
Number Of Circuits
1
Voltage - Supply
1.8V, 3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
*
Includes
Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
Number Of Transceivers
1
Screening Level
Industrial
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Power (watts)
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
800-1703
82P2821BHG
82P2821BHG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82P2821BHG
Manufacturer:
IDT
Quantity:
170
Company:
Part Number:
IDT82P2821BHG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
LOS - LOS Configuration Register
Address: 00DH, 04DH, 08DH, 0CDH, 10DH, 14DH, 18DH, 1CDH, (CH1~CH8)
Type: Read / Write
Default Value: 15H
Programming Information
IDT82P2821
6 - 4
3 - 2
Bit
7
20DH, 24DH, 28DH, 2CDH, 30DH, 34DH, 38DH, 3CDH, (CH9~CH16)
40DH, 44DH, 48DH, 4CDH, 50DH, (CH17~CH21)
7CDH (CH0)
LAC
7
TALOS[1:0]
ALOS[2:0]
Name
LAC
ALOS2
6
This bit selects the LLOS, SLOS and AIS criteria.
0: T1.231 (in T1/J1 mode) / G.775 (in E1 mode). (default)
1: I.431 (in T1/J1 mode) / ETSI 300233 & I.431 (in E1 mode).
These bits select the amplitude threshold (Q). When the amplitude of the data is less than Q Vpp for N consecutive pulse inter-
vals, LLOS is declared. The consecutive pulse intervals (N) are determined by the LAC bit (b7, LOS,...).
The ALOS[2:0] settings for Normal Receive mode and Line Monitor mode are different. Refer to below tables.
These bits select the amplitude threshold. When the amplitude of the data is less than the threshold for a certain period, TLOS is
declared. The period is determined by the TDLOS bits (b1~0, LOS,...). When the amplitude of a pulse is above the threshold,
TLOS is cleared.
For Differential line interface:
00: 1.2 Vp.
01: 0.9 Vp. (default)
10: 0.6 Vp.
11: 0.4 Vp.
For Single Ended line interface:
00: 0.61 Vp.
01: 0.48 Vp. (default)
10: 0.32 Vp.
11: 0.24 Vp.
ALOS1
5
ALOS[2:0] Setting in Normal Receive Mode
ALOS[2:0] Setting in Line Monitor Mode
001 (default)
001 (default)
ALOS[2:0]
ALOS[2:0]
000
010
011
100
101
110
000
010
011
1xx
111
ALOS0
4
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
97
Q (Vpp)
Q (Vpp)
0.5
0.7
0.9
1.2
1.4
1.6
1.8
2.0
1.0
1.4
1.8
2.2
TALOS1
3
Description
vs. 6.0 Vpp (dB)
vs. 6.0 Vpp (dB)
reserved.
TALOS0
21.58
18.66
16.48
13.98
12.64
11.48
10.46
15.56
12.64
10.46
9.54
8.71
2
vs. 4.74 Vpp (dB)
vs. 4.74 Vpp (dB)
TDLOS1
19.54
16.61
14.43
11.93
10.59
13.52
10.59
9.43
8.41
7.49
8.41
6.67
1
February 6, 2009
TDLOS0
0