C8051F317-GMR Silicon Laboratories Inc, C8051F317-GMR Datasheet - Page 109

• Manufacturer Part Number: C8051F317-GMR
• Description: MCU 8-Bit C8051F31x 8051 CISC 16KB Flash 3.3V 24-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F317-GMR

• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F31x
• Maximum Speed: 25 MHz
• Ram Size: 1.25 KB
• Program Memory Size: 16 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 21
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 17-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
Note:
Bit7
R
-
UNUSED. Read = 0. Write = don’t care.
FERROR: Flash Error Indicator.
0: Source of last reset was not a Flash read/write/erase error.
1: Source of last reset was a Flash read/write/erase error.
C0RSEF: Comparator0 Reset Enable and Flag.
0: Read: Source of last reset was not Comparator0. Write: Comparator0 is not a reset
source.
1: Read: Source of last reset was Comparator0. Write: Comparator0 is a reset source
(active-low).
SWRSF: Software Reset Force and Flag.
0: Read: Source of last reset was not a write to the SWRSF bit. Write: No Effect.
1: Read: Source of last was a write to the SWRSF bit. Write: Forces a system reset.
WDTRSF: Watchdog Timer Reset Flag.
0: Source of last reset was not a WDT timeout.
1: Source of last reset was a WDT timeout.
MCDRSF: Missing Clock Detector Flag.
0: Read: Source of last reset was not a Missing Clock Detector timeout. Write: Missing
Clock Detector disabled.
1: Read: Source of last reset was a Missing Clock Detector timeout. Write: Missing Clock
Detector enabled; triggers a reset if a missing clock condition is detected.
PORSF: Power-On Reset Force and Flag.
This bit is set anytime a power-on reset occurs. Writing this bit enables/disables the V
monitor as a reset source. Note: writing ‘1’ to this bit before the V
and stabilized may cause a system reset. See register VDM0CN (Figure 9.1)
0: Read: Last reset was not a power-on or V
reset source.
1: Read: Last reset was a power-on or V
Write: V
PINRSF: HW Pin Reset Flag.
0: Source of last reset was not RST pin.
1: Source of last reset was RST pin.
For bits that act as both reset source enables (on a write) and reset indicator flags (on a read),
read-modify-write instructions read and modify the source enable only. This applies to bits:
C0RSEF, SWRSF, MCDRSF, PORSF.
FERROR C0RSEF
Bit6
R
DD
monitor is a reset source.
SFR Definition 9.2. RSTSRC: Reset Source
R/W
Bit5
SWRSF
R/W
Bit4
WDTRSF MCDRSF
Rev. 1.7
Bit3
DD
R
monitor reset; all other reset flags indeterminate.
C8051F310/1/2/3/4/5/6/7
DD
monitor reset. Write: V
R/W
Bit2
PORSF
R/W
Bit1
DD
SFR Address:
DD
PINRSF
monitor is enabled
Bit0
monitor is not a
R
0xEF
Reset Value
Variable
DD
109