C8051F317-GMR Silicon Laboratories Inc, C8051F317-GMR Datasheet - Page 226
C8051F317-GMR
Manufacturer Part Number
C8051F317-GMR
Description
MCU 8-Bit C8051F31x 8051 CISC 16KB Flash 3.3V 24-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F310-TB.pdf
(228 pages)
Specifications of C8051F317-GMR
Package
24QFN EP
Device Core
8051
Family Name
C8051F31x
Maximum Speed
25 MHz
Ram Size
1.25 KB
Program Memory Size
16 KB
Operating Supply Voltage
3.3 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
21
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
17-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F317-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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C8051F310/1/2/3/4/5/6/7
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Revision 1.5 to Revision 1.6
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Revision 1.6 to Revision 1.7
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226
OCUMENT
Added two part numbers: C8051F316 and C8051F317
Changed package nomenclature from MLP to QFN.
Chapter 1.“System Overview”: Updated Table 1.1, “Product Selection Guide,” on page 18, with new
ordering part numbers; added block diagrams for the new parts, and updated Figure 1.13.
Added Table 3.2, “Electrical Characteristics Quick Reference,” on page 38.
Chapter 4.“Pinout and Package Definitions”: Updated Table 4.1 and added package diagrams for the
new parts.
Chapter 5.“10-Bit ADC (ADC0, C8051F310/1/2/3/6 only)”: Updated Figure 5.1, SFR Definition 5.1, and
SFR Definition 5.2 to show behavior of new parts.
Chapter 9.“Reset Sources”: Added note to SFR Definition 9.2 describing the behavior of read-modify-
write instructions on this register; Corrected Max VDD Ramp Time to 1 mS.
Chapter 10.“Flash Memory”: Updated Table 10.1 to accommodate the new parts; Added Table 10.2,
“Flash Security Summary,” on page 114 for clarity, replacing the Flash security summaries text.
Chapter 13.“Port Input/Output”: Updated text, Figure 13.1, Figure 13.3, Figure 13.4, and SFR Defini-
tion 13.7 through SFR Definition 13.17 to accommodate the new part numbers.
Chapter 18.“Programmable Counter Array”: In Table 18.3, corrected internal oscillator reset frequency
from 3,060,000 Hz to 3,062,500 Hz.
Chapter 20.“C2 Interface”: Updated C2 Register Definition 20.2 to accommodate the new part num-
bers. Corrected Device ID that is common to all 'F31x devices from 0x09 to 0x08; Removed references
to "boundary scan" because this feature is not supported by the 'F31x devices.
Fixed various minor errors.
Updated values in Table 3.1, “Global DC Electrical Characteristics,” on page 36.
Added Section
C
“10.4. Flash Write and Erase
HANGE
L
IST
Rev. 1.7
Guidelines” on page 115.
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