C8051F317-GMR Silicon Laboratories Inc, C8051F317-GMR Datasheet - Page 156
C8051F317-GMR
Manufacturer Part Number
C8051F317-GMR
Description
MCU 8-Bit C8051F31x 8051 CISC 16KB Flash 3.3V 24-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F310-TB.pdf
(228 pages)
Specifications of C8051F317-GMR
Package
24QFN EP
Device Core
8051
Family Name
C8051F31x
Maximum Speed
25 MHz
Ram Size
1.25 KB
Program Memory Size
16 KB
Operating Supply Voltage
3.3 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
21
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
17-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F317-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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C8051F310/1/2/3/4/5/6/7
14.4.3. Data Register
The SMBus Data register SMB0DAT holds a byte of serial data to be transmitted or one that has just been
received. Software may safely read or write to the data register when the SI flag is set. Software should not
attempt to access the SMB0DAT register when the SMBus is enabled and the SI flag is cleared to logic 0,
as the interface may be in the process of shifting a byte of data into or out of the register.
Data in SMB0DAT is always shifted out MSB first. After a byte has been received, the first bit of received
data is located at the MSB of SMB0DAT. While data is being shifted out, data on the bus is simultaneously
being shifted in. SMB0DAT always contains the last data byte present on the bus. In the event of lost arbi-
tration, the transition from master transmitter to slave receiver is made with the correct data or address in
SMB0DAT.
156
Bits7–0: SMB0DAT: SMBus Data.
R/W
Bit7
The SMB0DAT register contains a byte of data to be transmitted on the SMBus serial inter-
face or a byte that has just been received on the SMBus serial interface. The CPU can read
from or write to this register whenever the SI serial interrupt flag (SMB0CN.0) is set to
logic 1. The serial data in the register remains stable as long as the SI flag is set. When the
SI flag is not set, the system may be in the process of shifting data in/out and the CPU
should not attempt to access this register.
R/W
Bit6
SFR Definition 14.3. SMB0DAT: SMBus Data
R/W
Bit5
R/W
Bit4
Rev. 1.7
R/W
Bit3
R/W
Bit2
R/W
Bit1
SFR Address:
R/W
Bit0
0xC2
00000000
Reset Value
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