C8051F317-GMR Silicon Laboratories Inc, C8051F317-GMR Datasheet - Page 188

• Manufacturer Part Number: C8051F317-GMR
• Description: MCU 8-Bit C8051F31x 8051 CISC 16KB Flash 3.3V 24-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F317-GMR

• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F31x
• Maximum Speed: 25 MHz
• Ram Size: 1.25 KB
• Program Memory Size: 16 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 21
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 17-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

C8051F310/1/2/3/4/5/6/7
The C/T0 bit (TMOD.2) selects the counter/timer's clock source. When C/T0 is set to logic 1, high-to-low
transitions at the selected Timer 0 input pin (T0) increment the timer register (Refer to
“13.1. Priority Crossbar Decoder” on page 131
pins). Clearing C/T selects the clock defined by the T0M bit (CKCON.3). When T0M is set, Timer 0 is
clocked by the system clock. When T0M is cleared, Timer 0 is clocked by the source selected by the Clock
Scale bits in CKCON (see SFR Definition 17.3).
Setting the TR0 bit (TCON.4) enables the timer when either GATE0 (TMOD.3) is logic 0 or the input signal
/INT0 is active as defined by bit IN0PL in register IT01CF (see SFR Definition 8.11. “IT01CF: INT0/INT1
Configuration” on page 101). Setting GATE0 to ‘1’ allows the timer to be controlled by the external input
signal /INT0 (see
measurements.
Setting TR0 does not force the timer to reset. The timer registers should be loaded with the desired initial
value before the timer is enabled.
TL1 and TH1 form the 13-bit register for Timer 1 in the same manner as described above for TL0 and TH0.
Timer 1 is configured and controlled using the relevant TCON and TMOD bits just as with Timer 0. The
input signal /INT1 is used with Timer 1; the /INT1 polarity is defined by bit IN1PL in register IT01CF (see
SFR Definition 8.11. “IT01CF: INT0/INT1 Configuration” on page 101).
188
X = Don't Care
TR0
0
1
1
1
/INT0
T0
GATE0
Crossbar
X
0
1
1
Section “8.3.5. Interrupt Register Descriptions” on page
Pre-scaled Clock
SYSCLK
IN0PL
/INT0
Figure 17.1. T0 Mode 0 Block Diagram
GATE0
X
X
0
1
XOR
Counter/Timer
TR0
0
1
M
Disabled
Disabled
T
H
3
Enabled
Enabled
M
T
3
L
CKCON
M
T
H
2
T
M
2
L
0
1
T
M
1
M
T
0
Rev. 1.7
S
C
A
1
for information on selecting and configuring external I/O
S
C
A
0
G
A
T
E
1
C
T
1
/
M
T
1
1
TMOD
M
T
1
0
TCLK
G
A
T
E
0
C
T
0
/
M
T
0
1
M
T
0
0
(5 bits)
TL0
N
P
1
L
I
N
1
S
L
2
I
INT01CF
N
1
S
L
1
I
N
1
S
L
0
I
N
0
P
L
I
(8 bits)
TH0
N
0
S
L
2
I
N
0
S
L
1
I
N
S
0
L
0
I
97), facilitating pulse width
TR1
TR0
TF1
TF0
IE1
IE0
IT1
IT0
Interrupt
Section