SI3050-KT Silicon Laboratories Inc, SI3050-KT Datasheet - Page 24

• Manufacturer Part Number: SI3050-KT
• Description: IC VOICE DAA GCI/PCM/SPI 20TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: Chipsetr

Specifications of SI3050-KT

• Package / Case: 20-TSSOP
• Function: Data Access Arrangement (DAA)
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Product: Modem Chip
• Supply Voltage (min): 3 V
• Supply Current: 8.5 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Si3050
RCALD
calibration is also performed to remove offsets that
might be present in the on-chip A/D converter, which
could affect the A/D dynamic range. The ADC
auto-calibration is initiated after the DAA dc termination
stabilizes and the resistor calibration completes. Due to
the large variation in line conditions and line card
behavior presented to the DAA, it might be beneficial to
use manual ADC calibration instead of auto-calibration.
Manual ADC calibration should be executed as close as
possible to 256 ms before valid transmit/receive data is
expected.
The following steps should be taken to implement
manual ADC calibration:
1. The CALD bit (auto-calibration disable—Register 17) must
2. The MCAL bit (manual calibration) must be toggled to one
3. The calibration is completed in
In-Circuit Testing
The Si3050’s advanced design provides the designer
with
functionality during production line tests and support for
end-user diagnostics. Six loopback modes allow
increased coverage of system components. For four of
the test modes, a line-side power source is needed.
While a standard phone line can be used, the test circuit
in Figure 1 on page 6 is adequate. In addition, an
off-hook sequence must be performed to connect the
power source to the line-side device.
For the start-up loopback test mode, no line-side power
is necessary, and no off-hook sequence is required. The
start-up test mode is enabled by default. When the PDL
bit (Register 6, bit 4) is set (the default case), the line
side is in a powerdown mode, and the system-side is in
a digital loopback mode. In this mode, data received on
DRX passes through the internal filters and is
transmitted on DTX. This path introduces approximately
0.9 dB of attenuation on the DRX signal received. The
group delay of both transmit and receive filters exists
between DRX and DTX. Clearing the PDL bit disables
this mode, and the DTX data switches to the receive
data from the line side. When the PDL bit is cleared, the
FDT bit (Register 12, bit 6) becomes active to indicate
that successful communication between the line side
and system
verification that the ISOcap link is operational.
The digital data loop-back mode offers a way to input
data on the DRX pin and have the identical data be
output on the DTX pin by bypassing the transmit and
receive filters. Setting the DDL bit (Register 10, bit 0)
24
be set to 1.
and then 0 to begin and complete the calibration.
an
bit
increased
(Register 25, bit 5).
side
is
ability
established.
256 ms
to
determine
A
.
This provides
256 ms
system
ADC
Rev. 1.0
enables this mode, which provides an easy way to verify
communication between the host processor/DSP and
the DAA. No line-side power or off-hook sequence is
required for this mode.
The remaining test modes require an off-hook sequence
to operate. The following sequence lists the off-hook
requirements:
1. Powerup or reset.
2. Allow the internal PLL to lock on PCLK and FSYNC.
3. Enable line-side by clearing PDL bit.
4. Issue off-hook.
5. Delay 402.75 ms for calibration to occur.
6. Set desired test mode.
The ISOcap digital loopback mode allows the host
processor to provide a digital input test pattern on DRX
and receive that digital test pattern back on DTX. To
enable this mode, set the IDL bit (Register 1, bit 1). The
isolation barrier is tested in this mode. The digital
stream is delivered across the isolation capacitors, C1
and C2, of the "Typical Application Schematic" on page
17, to the line-side device and returned across the same
barrier. In the ISOcap digital loopback mode, the 0.9 dB
attenuation and filter group delays also exist.
The analog loopback mode allows an external device to
drive a signal on the telephone line into the line-side
device and drive it back onto the line. This mode allows
testing of external components connecting the RJ-11
jack (TIP and RING) to the line-side device. To enable
this mode, set the AL bit (Register 2, bit 3).
The PCM analog loopback mode extends the signal
path of the analog loopback mode. In this mode, an
analog signal can be driven from the line into the
line-side device. This analog signal is converted to
digital data and then passed across the isolation barrier
capacitors to the system-side device. The data passes
through the receive filter, is routed back through the
transmit filter, and is then passed back across the
isolation barrier and sent back out onto the line as an
analog signal. Set the PCML bit (Register 33, bit 7) to
enable this mode.
With the final testing mode, internal analog loopback,
the system can test the basic operation of the transmit
and receive paths on the line-side device and the
external components in the "Typical Application
Schematic" on page 17. The host provides a digital test
waveform on DRX. Data passes across the isolation
barrier, is transmitted to and received from the line,
passes back across the isolation barrier, and is
presented to the host on DTX. Clear the HBE bit
(Register 2, bit 1) to enable this mode.
When the HBE bit is cleared, it produces a dc offset that