SI3050-KT Silicon Laboratories Inc, SI3050-KT Datasheet - Page 30

• Manufacturer Part Number: SI3050-KT
• Description: IC VOICE DAA GCI/PCM/SPI 20TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: Chipsetr

Specifications of SI3050-KT

• Package / Case: 20-TSSOP
• Function: Data Access Arrangement (DAA)
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Product: Modem Chip
• Supply Voltage (min): 3 V
• Supply Current: 8.5 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Si3050
impedance network for trunks. The last ac termination
selection, ACIM[3:0] = 1111, is designed to satisfy
minimum return loss requirements for every country that
requires a complex termination. By selecting this
setting, the system is ensured to meet minimum PTT
requirements.
For each of the sixteen ac termination settings, the
programmable digital hybrid can be used to further
reduce near-end echo. See "Transhybrid Balance" on
page 36 for details.
Ring Detection
The ring signal is resistively coupled from TIP and RING
to the RNG1 and RNG2 pins. The Si3050 supports
either full- or half-wave ring detection. With full-wave
ring detection, the designer can detect a polarity
reversal of the ring signal. See “Caller ID” on page 33.
The ring detection threshold is programmable with the
RT bit (Register 16, bit 0) and RT2 bit (Register 17,
bit 4). The ring detector output can be monitored in
three ways. The first method uses the RGDT pin. The
second method uses the register bits, RDTP, RDTN,
and RDT (Register 5). The final method uses the DTX
output.
The ring detector mode is controlled by the RFWE bit
(Register 18, bit 1). When the RFWE bit is 0 (default
mode), the ring detector operates in half-wave rectifier
mode. In this mode, only positive ring signals are
30
ACIM[3:0]
Table 18. AC Termination Settings for the
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
1011
1100
1101
0111
1110
1111
Si3019 Line-Side Device
600 Ω
900 Ω
270 Ω + (750 Ω || 150 nF) and
275 Ω + (780 Ω || 150 nF)
220 Ω + (820 Ω || 120 nF) and 220 Ω
+ (820 Ω || 115 nF)
370 Ω + (620 Ω || 310 nF)
320 Ω + (1050 Ω || 230 nF)
370 Ω + (820 Ω || 110 nF)
275 Ω + (780 Ω || 150 nF)
120 Ω + (820 Ω || 110 nF)
350 Ω + (1000 Ω || 210 nF)
0 Ω + (900 Ω || 30 nF)
600 Ω + 2.16 µ F
900 Ω + 1 µ F
900 Ω + 2.16 µ F
600 Ω + 1 µ F
Global complex impedance
AC Termination
Rev. 1.0
detected. A positive ring signal is defined as a voltage
greater than the ring threshold across RNG1-RNG2.
Conversely, a negative ring signal is defined as a
voltage less than the negative ring threshold across
RNG1-RNG2. When the RFWE bit is 1, the ring detector
operates in full-wave rectifier mode. In this mode, both
positive and negative ring signals are detected.
The first method to monitor ring detection output uses
the RGDT pin. When the RGDT pin is used, it defaults
to active low, but can be changed to active high by
setting the RPOL bit (Register 14, bit 1). This pin is an
open-drain output, and requires a 4.7 k Ω pullup or
pulldown for correct operation. If multiple RGDT pins
are connected to a single input, the combined pullup or
pulldown resistance should equal 4.7 k Ω.
When the RFWE bit is 0, the RGDT pin is asserted
when the ring signal is positive, which results in an
output signal frequency equal to the actual ring
frequency. When the RFWE bit is 1, the RGDT pin is
asserted when the ring signal is positive or negative.
The output then appears to be twice the frequency of
the ring waveform.
The second method to monitor ring detection uses the
ring detect bits (RDTP, RDTN, and RDT). The RDTP
and RDTN behavior is based on the RNG1-RNG2
voltage. When the signal on RNG1-RNG2 is above the
positive ring threshold, the RDTP bit is set. When the
signal on RNG1-RNG2 is below the negative ring
threshold, the RDTN bit is set. When the signal on
RNG1-RNG2 is between these thresholds, neither bit is
set.
The RDT behavior is also based on the RNG1-RNG2
voltage. When the RFWE bit is 0, a positive ring signal
sets the RDT bit for a period of time. When the RFWE
bit is 1, a positive or negative ring signal sets the RDT
bit.
The RDT bit acts like a one shot. When a new ring
signal is detected, the one shot is reset. If no new ring
signals are detected prior to the one shot counter
reaching 0, then the RDT bit clears. The length of this
count is approximately 5 seconds. The RDT bit is reset
to 0 by an off-hook event. If the RDTM bit
(Register 3, bit 7) is set, a hardware interrupt occurs on
the AOUT/INT pin when RDT is triggered. This interrupt
can
(Register 4, bit 7). When the RDI bit (Register 2, bit 2) is
set, an interrupt occurs on both the beginning and end
of the ring pulse as defined by the RTO bits
(Register 23, bits 6:3).
enabled when using the RDI bit.
The third method to monitor detection uses the DTX
data samples to transmit ring data. If the ISOcap is
be
cleared
by
Ring
writing
validation
to
the
should
RDTI
be
bit