SI3050-KT Silicon Laboratories Inc, SI3050-KT Datasheet - Page 40

• Manufacturer Part Number: SI3050-KT
• Description: IC VOICE DAA GCI/PCM/SPI 20TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: Chipsetr

Specifications of SI3050-KT

• Package / Case: 20-TSSOP
• Function: Data Access Arrangement (DAA)
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Product: Modem Chip
• Supply Voltage (min): 3 V
• Supply Current: 8.5 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

Si3050
Companding in PCM Mode
The
companding formats in addition to 16-bit linear data.
The 8-bit companding schemes follow a segmented
curve formatted as a sign bit, three chord bits, and four
step bits. µ-Law is commonly used in North America
and Japan, while A-Law is primarily used in Europe.
Data format is selected via the PCMF bits (Register 33).
Table 22 on page 41 and Table 23 on page 42 define
the µ-Law and A-Law encoding formats. If linear mode
is used the resulting 16-bit data is transmitted in two
consecutive 8-bit PCM highway timeslots as shown in
Figure 32.
40
PCLK_CNT
FSYNC
PCLK
DRX
DTX
Si3050
PCLK_CNT
HI-Z
FSYNC
Figure 32. PCM Highway Transmission, Single Clock Cycle, 16-bit linear mode
Figure 33. PCM Highway Transmission, Single Clock Cycle, 16-bit linear mode
PCLK
0
DRX
DTX
MSB
MSB
1
supports
2
HI-Z
3
4
0
5
(TXS=RXS=0, PHCF= 0, TRI=1, PCMF=11, HSSM=1)
both
MSB
MSB
6
1
Sample 1
7
(TXS=RXS=0, PHCF= 0, TRI=1, PCMF=11)
2
8
µ-Law
9
3
10
11
4
12
and
5
13
14
A-Law
6
15
16
Rev. 1.0
7
17
8
16 kHz Sampling Operation in PCM Mode
The Si3050 can be configured to support a 16 kHz
sampling rate and transmit the data on an 8 kHz PCM or
GCI
(Register 7, bit 3) to 1, the DAA changes its sampling
rate, Fs, to 16 kHz if it was originally configured for an
8 kHz sampling rate. If µ-law or A-law companding is
used, the resulting 8-bit samples are transmitted in two
consecutive 8-bit PCM highway timeslots. If linear mode
is used, the resulting 16-bit samples are transmitted in
four consecutive 8-bit PCM highway timeslots as shown
in Figure 33.
18
19 20
9
highway
10
21
22
11
Sample 2
23
12
24
bus.
HI-Z
25
13
26
27
14
By
28
15
29
setting
30
LSB
16
LSB
LSB
LSB
31
32
17
33
the
18
34
HI-Z
35
HSSM
36 37
bit