SI3050-KT Silicon Laboratories Inc, SI3050-KT Datasheet - Page 69

IC VOICE DAA GCI/PCM/SPI 20TSSOP

SI3050-KT

Manufacturer Part Number
SI3050-KT
Description
IC VOICE DAA GCI/PCM/SPI 20TSSOP
Manufacturer
Silicon Laboratories Inc
Type
Chipsetr
Datasheets

Specifications of SI3050-KT

Package / Case
20-TSSOP
Function
Data Access Arrangement (DAA)
Interface
PCM, Serial, SPI
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Product
Modem Chip
Supply Voltage (min)
3 V
Supply Current
8.5 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power (watts)
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

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Register 16. International Control 1
Reset settings = 0000_0000
Name
3:2
Bit
Type
7
6
5
4
1
0
Bit
Reserved This bit may be written to a zero or one.
Reserved
Reserved
Name
OHS
IIRE
D7
RZ
RT
OHS
R/W
D6
On-Hook Speed.
This bit, in combination with the OHS2 bit (Register 31) and the SQ[1:0] bits (Register 59), sets
the amount of time for the line-side device to go on-hook. The on-hook speeds specified are
measured from the time the OH bit is cleared until loop current equals zero.
OHS
IIR Filter Enable.
0 = FIR filter enabled for transmit and receive filters. (See Figures 7–10 on page 15.)
1 = IIR filter enabled for transmit and receive filters. (See Figures 11–16 on page 16.)
Ringer Impedance.
0 = Maximum (high) ringer impedance.
1 = Synthesized ringer impedance used to satisfy a maximum ringer impedance specification
in countries, such as Poland, South Africa, and Slovenia.
Ringer Threshold Select.
This bit, in combination with the RT2 bit, is used to satisfy country requirements on ring detec-
tion. Signals below the lower level do not generate a ring detection; signals above the upper
level are guaranteed to generate a ring detection.
RT
0
0
1
1
This bit may be written to a zero or one.
Read returns zero.
0
0
1
D5
OHS2
IIRE
R/W
D4
0
1
X
RT2
0
1
0
1
D3
SQ[1:0]
RT Lower level
13.5 V
Reserved, do not use this setting.
19.35 V
40.5 V
00
00
11
D2
rms
rms
Rev. 1.0
rms
R/W
Mean On-Hook Speed
D1
RZ
26 ms ±10% (meets Australia spark quenching spec)
Less than 0.5 ms
3 ms ±10% (meets ETSI standard)
Function
RT Upper level
16.5 V
23.65 V
49.5 V
R/W
RT
D0
rms
rms
rms
Si3050
69

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