DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet - Page 6

• Manufacturer Part Number: DS21Q55
• Description: IC TXRX QUAD T1/E1/J1 SCT 256BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q55

• Function: Transceiver
• Interface: E1, J1, T1
• Number Of Circuits: 4
• Voltage - Supply: 3.14 V ~ 3.47 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Includes: BERT Generator and Detector, Dual HDLC Controllers
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -

DS21Q55 Quad T1/E1/J1 Transceiver
TABLE OF FIGURES
Figure 1-1. Block Diagram ..........................................................................................................................................14
Figure 1-2. Receive and Transmit LIU........................................................................................................................15
Figure 1-3. Receive and Transmit Framer/HDLC.......................................................................................................16
Figure 1-4. Backplane Interface..................................................................................................................................17
Figure 2-1. DS21Q55 PIN DIAGRAM, 27mm BGA ....................................................................................................35
Figure 5-1. Programming Sequence ..........................................................................................................................45
Figure 6-1. Clock Map ................................................................................................................................................49
Figure 14-1. Simplified Diagram of Receive Signaling Path.......................................................................................87
Figure 14-2. Simplified Diagram of Transmit Signaling Path......................................................................................93
Figure 18-1. CRC-4 Recalculate Method .................................................................................................................113
Figure 22-1. Typical Monitor Application ..................................................................................................................148
Figure 22-2. CMI Coding ..........................................................................................................................................150
Figure 22-3. Basic Interface......................................................................................................................................160
Figure 22-4. Protected Interface Using Internal Receive Termination .....................................................................161
Figure 22-5. E1 Transmit Pulse Template................................................................................................................163
Figure 22-6. T1 Transmit Pulse Template ................................................................................................................163
Figure 22-7. Jitter Tolerance.....................................................................................................................................164
Figure 22-8. Jitter Tolerance (E1 Mode)...................................................................................................................164
Figure 22-9. Jitter Attenuation (T1 Mode).................................................................................................................165
Figure 22-10. Jitter Attenuation (E1 Mode) ..............................................................................................................165
Figure 24-1. Simplified Diagram of BERT in Network Direction ...............................................................................174
Figure 24-2. Simplified Diagram of BERT in Backplane Direction ...........................................................................174
Figure 26-1. IBO Example ........................................................................................................................................189
Figure 27-1. ESIB Group of Two DS21Q55s............................................................................................................190
Figure 30-1. JTAG Functional Block Diagram ..........................................................................................................198
Figure 30-2. TAP Controller State Diagram..............................................................................................................201
Figure 31-1. Receive-Side D4 Timing ......................................................................................................................207
Figure 31-2. Receive-Side ESF Timing ....................................................................................................................207
Figure 31-3. Receive-Side Boundary Timing (with elastic store disabled) ...............................................................208
Figure 31-4. Receive-Side 1.544MHz Boundary Timing (with Elastic Store Enabled).............................................208
Figure 31-5. Receive-Side 2.048MHz Boundary Timing (with Elastic Store Enabled).............................................209
Figure 31-6. Transmit-Side D4 Timing .....................................................................................................................209
Figure 31-7. Transmit-Side ESF Timing ...................................................................................................................210
Figure 31-8. Transmit-Side Boundary Timing (with Elastic Store Disabled) ............................................................210
Figure 31-9. Transmit-Side 1.544MHz Boundary Timing (with Elastic Store Enabled)............................................211
Figure 31-10. Transmit-Side 2.048MHz Boundary Timing (with Elastic Store Enabled)..........................................211
Figure 31-11. Receive-Side Timing ..........................................................................................................................212
Figure 31-12. Receive-Side Boundary Timing (with Elastic Store Disabled) ...........................................................212
Figure 31-13. Receive-Side Boundary Timing, RSYSCLK = 1.544MHz (Elastic Store Enabled) ............................213
Figure 31-14. Receive-Side Boundary Timing, RSYSCLK = 2.048MHz (Elastic Store Enabled) ............................213
Figure 31-15. Receive IBO Channel Interleave Mode Timing..................................................................................214
Figure 31-16. Receive IBO Frame Interleave Mode Timing.....................................................................................215
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