DS21Q55 Maxim Integrated Products, DS21Q55 Datasheet - Page 8
![IC TXRX QUAD T1/E1/J1 SCT 256BGA](/photos/6/82/68222/406-256-bga_sml.jpg)
DS21Q55
Manufacturer Part Number
DS21Q55
Description
IC TXRX QUAD T1/E1/J1 SCT 256BGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS21Q55.pdf
(237 pages)
Specifications of DS21Q55
Function
Transceiver
Interface
E1, J1, T1
Number Of Circuits
4
Voltage - Supply
3.14 V ~ 3.47 V
Current - Supply
75mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Includes
BERT Generator and Detector, Dual HDLC Controllers
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power (watts)
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DS21Q552
Manufacturer:
DALLAS
Quantity:
319
Company:
Part Number:
DS21Q552BN+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS21Q554
Manufacturer:
DALLAS
Quantity:
20 000
Part Number:
DS21Q554B+
Manufacturer:
MAXIM/美信
Quantity:
20 000
DS21Q55 Quad T1/E1/J1 Transceiver
TABLE OF TABLES
Table 2-A. Pin Description Sorted by Pin Number .....................................................................................................29
Table 3-A. Register Map Sorted by Address ..............................................................................................................36
Table 7-A. T1 Alarm Criteria .......................................................................................................................................58
Table 8-A. E1 Sync/Resync Criteria ...........................................................................................................................60
Table 8-B. E1 Alarm Criteria.......................................................................................................................................65
Table 12-A. T1 Line Code Violation Counting Options...............................................................................................80
Table 12-B. E1 Line-Code Violation Counting Options ..............................................................................................80
Table 12-C. T1 Path Code Violation Counting Arrangements....................................................................................82
Table 12-D. T1 Frames Out-of-Sync Counting Arrangements ...................................................................................83
Table 14-A. Time Slot Numbering Schemes ..............................................................................................................94
Table 15-A. Idle-Code Array Address Mapping........................................................................................................100
Table 15-B. GRIC and GTIC Functions ....................................................................................................................102
Table 17-A. Elastic Store Delay After Initialization ...................................................................................................112
Table 21-A. HDLC Controller Registers ...................................................................................................................131
Table 22-A. Transformer Specifications ...................................................................................................................162
Table 25-A. Transmit Error-Insertion Setup Sequence ............................................................................................183
Table 25-B. Error Insertion Examples ......................................................................................................................185
Table 30-A. Instruction Codes for IEEE 1149.1 Architecture ...................................................................................202
Table 30-B. ID Code Structure .................................................................................................................................203
Table 30-C. Device ID Codes ...................................................................................................................................203
Table 30-D. Boundary Scan Control Bits..................................................................................................................204
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