PEB20320H-V34RF Infineon Technologies, PEB20320H-V34RF Datasheet - Page 252

• Manufacturer Part Number: PEB20320H-V34RF
• Description: IC CONTROLR 32-CH HDLC 160-MQFP
• Manufacturer: Infineon Technologies

Specifications of PEB20320H-V34RF

• Function: Multichannel Network Interface Controller (MUNICH)
• Interface: HDLC, ISDN, V.110, X.30
• Voltage - Supply: 5V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BSQFP
• Includes: Automatic Flag Detection, CRC Generation and Checking, Error Detection, Interframe-Time-Fill Change Detection
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Power (watts): -
• Number Of Circuits: -
• Other names: PEB20320H-V34RF; PEB20320H-V34RFIN

User’s Manual
/*--------------------------------------------------------------------------
*/
static
{
*/
}
- Function
--------------------------------------------------------------------------
- Description :
--------------------------------------------------------------------------
/*=== Transmit Descriptor ===============================================*/
channelControl[0].lasttxdescr ->next = txDescr; /* Add frame to existing */
channelControl[0].lasttxdescr
m32TxDescr = txDescr;
channelControl[0].lasttxdescr ->hold = 0;
txDescr ->fe
txDescr ->hold
-------------------------------------------------------------------------
for ( ; txDescr ->next; txDescr
{
}
..
..
txDescr ->hi
txDescr ->fnum
txDescr ->hold
txDescr ->fe
txDescr ->v110
void
:
TxHdlcFrame
Transmit an HDLC frame via channel 0
TxHdlcFrame ( MUNICH_TX_DESCR_PTR m32TxDescr )
= 0;
= 3;
= 0;
= 0;
= 0;
= 1;
= 1;
= txDescr; /* store last transmit pointer */
= txDescr ->next )
/* clear host initiated interrupt bit */
252
/* 3 interframe timefill char
/* clear frame end bit
/* set frame end bit
/* clear hold bit
/* clear v110 bit
/* set hold bit
/* store transmit descriptor pointer */
/* will then detect the
/* cleared hold bit and
/* send the following
/* the polling MUNICH32
/* frame
/* channel0 frame queue
PEB 20320
Appendix
01.2000
-
-
/*
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/
*/