SC28L202A1DGG,129 NXP Semiconductors, SC28L202A1DGG,129 Datasheet - Page 36
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SC28L202A1DGG,129
Manufacturer Part Number
SC28L202A1DGG,129
Description
IC DUART 3.3V-5.0V 56-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L202A1DGG118.pdf
(77 pages)
Specifications of SC28L202A1DGG,129
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
56-TFSOP (0.240", 6.10mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935276109129
Philips Semiconductors
TxFIL – Transmitter FIFO Interrupt Level A and B
The position in the Tx FIFO that caused the transmitter will enter the interrupt arbitration process. This register is used to offset the effect of the
arbitration threshold. It use may yield moderate improvements in the interrupt service. It will also ‘equalize’ interrupt latency and allow for larger
aggregate block transfers between fast and slow channels. Writing to this register removes the interrupt control established in MR0 and MR1.
TxEL – Transmitter FIFO Empty Level Register
The number of empty bytes in the Transmitter FIFO.
Registers for Character Recognition
Please not that, although the names of the registers imply a particular function, there is not any hardware function directly attached to them.
They are just three characters that may be used for any function requiring recognition or simple character stripping.
It is only when other internal logic is enabled that the reception of a recognized character will trigger particular chip functions and/or interrupts.
XonCR – Xon/Xoff Character Register A and B
An 8-bit character register that contains the compare value for a Xon character.
XoffCR – Xoff Character Register A and B
An 8-bit character register that contains the compare value for a Xoff character.
ARCR – Address Recognition Character Register A and B
An 8 bit character register that contains the compare value for the wake-up address character.
2005 Nov 01
Bits 7:0
Any one of 256 FIFO empty positions
Bits 7:0
Channel byte count code ** (1) = implied ‘1’
00000001 = 1
00000010 = 2
to
11111111 = 255
**(1)00000000 = 256 if TxRDY status bit is set.
Dual UART
Bits 7:0
8 Bits of the Xon Character Recognition (Resets to 0x11)
Bits 7:0
8 Bits of the Xoff Character Recognition (Resets to 0x13)
Bits 7:0
8 Bits of the Multi-Drop Address Character Recognition (Resets to 0x00)
30
SC28L202
Product data sheet