SC28L202A1DGG,129 NXP Semiconductors, SC28L202A1DGG,129 Datasheet - Page 62
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SC28L202A1DGG,129
Manufacturer Part Number
SC28L202A1DGG,129
Description
IC DUART 3.3V-5.0V 56-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L202A1DGG118.pdf
(77 pages)
Specifications of SC28L202A1DGG,129
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
56-TFSOP (0.240", 6.10mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935276109129
Philips Semiconductors
AC CHARACTERISTICS
V
2005 Nov 01
Symbol
Reset timing (See Figures 4, 5)
t
Bus Timing
t
t
t
t
t
t
t
t
t
t
t
t
Port Timing
t
t
t
Interrupt Timing (See Figure 11)
t
Clock Timing (See Figures 12, 13, 14)
t
f
t
f
t
f
t
f
Transmitter Timing (See Figures 13, 15)
t
t
Receiver Timing (See Figures 14, 16)
t
t
CC
RES
AS
AH
CS
CH
RW
DD
DA
DF
DI
DS
DH
RWD
PS
PH
PD
IR
CLK
CLK
CTC
CTC
RX
RX
TX
TX
TXD
TCS
RXS
RXH
Dual UART
= 5 V
10%; T
5
5
(See Figure 6)
(See Figure 10)
Parameter
Reset Pulse Width
A6–A0 set-up time to RDN, WRN Low
A6–A0 hold time from RDN, WRN low
CEN set-up time from RDN. WRN LOW
CEN hold time from RDN. WRN HIGH
WRN, RDN pulse width (Low time)
Data valid after RDN low (85 pf load)
RDN low to data bus active
Data bus floating after RDN or CEN high
RDN or CEN high to data bus invalid
Data bus set-up time before WRN or CEN high (write cycle)
Data hold time after WRN high
High time between read and/or write cycles
Port in set-up time before RDN low (Read IP ports cycle)
Port in hold time after RDN high
OP port valid after WRN or CEN high (OPR write cycle)
INTRN (or I/O[7:3]B when used as interrupts) negated from:
X1/SCLK high or low time
X1/SCLK frequency (7.0 to 16.2 MHz with crystal)
C/T Clk (IP2) high or low time (C/T external clock input)
C/T Clk (IP2) frequency
RxC high or low time (16X)
RxC Frequency (16X)
RxC Frequency (1x)
TxC High or low time (16X)
TxC frequency (16X)
TxC frequency (1X)
TxD output delay from TxC low (TxC input pin)
Output delay from TxC output pin low to TxD data output
RxD data set-up time to RxC high
RxD data hold time from RxC high
Read RxFIFO (RxRDY/FFULL interrupt)
Write TxFIFO (TxRDY interrupt)
Reset Command (delta break change interrupt)
Stop C/T command (Counter/timer interrupt
Read IPCR (delta input port change interrupt)
Write IMR (Clear of change interrupt mask bit(s))
amb
= – 40 C to +85 C unless otherwise specified.
1, 2, 3
8,9
8,9
(NOMINAL 5 V)
8
6
7
5,7
56
LIMITS
Min
100
10
10
0
0
30
–
0
–
0
15
0
10
0
0
–
–
–
–
–
–
–
8
1.0
10
0
8
0
0
8
–
0
–
–
20
20
4
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
SC28L202
Max
–
–
–
–
–
–
30
–
15
–
–
–
–
–
–
30
30
30
30
30
30
30
–
50
–
20
–
50
3
–
50
3
30
30
–
–
Product data sheet
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
ns
ns
ns
ns