SC28L202A1DGG,129 NXP Semiconductors, SC28L202A1DGG,129 Datasheet - Page 58
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SC28L202A1DGG,129
Manufacturer Part Number
SC28L202A1DGG,129
Description
IC DUART 3.3V-5.0V 56-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L202A1DGG118.pdf
(77 pages)
Specifications of SC28L202A1DGG,129
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
56-TFSOP (0.240", 6.10mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935276109129
Philips Semiconductors
REGISTER MAP
NOTE: The register maps for channels A and B (UARTs A and B) contain some control registers that configure the entire chip.
These are denoted by a ‘ ’ symbol
2005 Nov 01
A[6:0]
010 0000 (0x20)
010 0001 (0x21)
010 0010 (0x22)
010 0011 (0x23)
010 0100 (0x24)
010 0101 (0x25)
010 0110 (0x26)
010 0111 (0x27)
010 1000 (0x28)
010 1001 (0x29)
010 1010 (0x2A)
010 1011 (0x2B)
010 1100 (0x2C)
010 1101 (0x2D)
010 1110 (0x2E)
010 1111 (0x2F)
011 0000 (0x30)
011 0001 (0x31)
011 0010 (0x32)
011 0011 (0x33)
011 0100 (0x34)
011 0101 (0x35)
011 0110 (0x36)
011 0111 (0x37)
011 1000 (0x38)
011 1001 (0x39)
011 1010 (0x3A)
011 1011 (0x3B)
011 1100 (0x3C)
011 1101 (0x3D)
011 1110 (0x3E)
011 1111 (0x3F)
Dual UART
READ
EXTENSION
Mode Register 0 (MR0 A) NEW ADDRESS
Mode Register 1 (MR1 A) NEW ADDRESS
Mode Register 2 (MR2 A) NEW ADDRESS
Mode Register 3 (MR3 A) NEW ADDRESS
Counter/Timer Clock Source (CTCS 0)
Programmable BRG Preset Lower (PBRGPL 0)
Programmable BRG Preset Upper (PBRGPU 0)
Mode Register 0 (MR0 B) NEW ADDRESS
Mode Register 1 (MR1 B) NEW ADDRESS
Mode Register 2 (MR2 B) NEW ADDRESS
Mode Register 3 (MR3 B) NEW ADDRESS
Counter/Timer Clock Source (CTCS 1)
Interrupt Status Register (ISR B)
Receiver Clock Select Register (RxCSR A)
Transmitter Clock Select Register (TxCSR A)
Input Port Change Interrupt Enable (IPCE A)
Programmable BRG Clock Source (PBRGCS)
Programmable BRG Preset Lower (PBRGPL 1)
Programmable BRG Preset Upper (PBRGPU 1)
Receiver Clock Select Register (RxCSR B)
Transmitter Clock Select Register (TxCSR B)
Input Port Change Interrupt Enable (IPCE B)
Interrupt Status Register (ISR A)
52
WRITE
Mode Register 0 (MR0 A) NEW ADDRESS
Mode Register 1 (MR1 A) NEW ADDRESS
Mode Register 2 (MR2 A) NEW ADDRESS
Mode Register 3 (MR3 A) NEW ADDRESS
Counter/Timer Clock Source (CTCS 0)
Interrupt Mask Register (IMR A)
Programmable BRG Preset Lower (PBRGPL 0)
Programmable BRG Preset Upper (PBRGPU 0)
Mode Register 0 (MR0 B) NEW ADDRESS
Mode Register 1 (MR1 B) NEW ADDRESS
Mode Register 2 (MR2 B) NEW ADDRESS
Mode Register 3 (MR3 B) NEW ADDRESS
Counter/Timer Clock Source (CTCS 1)
Receiver Clock Select Register (RxCSR A)
Transmitter Clock Select Register (TxCSR A)
Input Port Change Interrupt Enable (IPCE A)
Programmable BRG Clock Source (PBRGCS)
Programmable BRG Preset Lower (PBRGPL 1)
Programmable BRG Preset Upper (PBRGPU 1)
Receiver Clock Select Register (RxCSR B)
Transmitter Clock Select Register (TxCSR B)
Input Port Change Interrupt Enable (IPCE B)
Interrupt Mask Register (IMR B)
SC28L202
Product data sheet