SC16C754IB80,528 NXP Semiconductors, SC16C754IB80,528 Datasheet - Page 14

• Manufacturer Part Number: SC16C754IB80,528
• Description: IC UART QUAD W/FIFO 80-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C754IB80,528

• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270057528; SC16C754IB80-T; SC16C754IB80-T

Philips Semiconductors
Table 6:
9397 750 11618
Product data
IIR[5:0]
000001
000110
001100
000100
000010
000000
010000
100000
Interrupt control functions
Priority
level
None
1
2
2
3
4
5
6
6.5 Interrupts
Interrupt type
none
receiver line status
RX time-out
RHR interrupt
THR interrupt
modem status
Xoff interrupt
CTS, RTS
The SC16C754 has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The interrupt enable register (IER) enables each of the six types
of interrupts and the INT signal in response to an interrupt generation. The IER can
also disable the interrupt system by clearing bits 0-3, 5-7. When an interrupt is
generated, the IIR indicates that an interrupt is pending and provides the type of
interrupt through IIR[5;0].
It is important to note that for the framing error, parity error, and break conditions,
LSR[7] generates the interrupt. LSR[7] is set when there is an error anywhere in the
RX FIFO, and is cleared only when there are no more errors remaining in the FIFO.
LSR[4:2] always represent the error status for the received character at the top of the
RX FIFO. Reading the RX FIFO updates LSR[4:2] to the appropriate status for the
new character at the top of the FIFO. If the RX FIFO is empty, then LSR[4:2] are all
zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the
interrupt is cleared by an Xon flow character detection. If a special character
detection caused the interrupt, the interrupt is cleared by a read of the LSR.
Interrupt source
none
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
stale data in RX FIFO
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level
(FIFO enable)
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger level
(FIFO enable)
MSR[3:0] = 0
receive Xoff character(s)/special
character
RTS pin or CTS pin change state from
active (LOW) to inactive (HIGH)
Rev. 04 — 19 June 2003
Table 6
summarizes the interrupt control functions.
Interrupt reset method
none
FE, PE, BI: all erroneous
characters are read from the
RX FIFO.
OE: read LSR
read RHR
read RHR
read IIR or a write to the THR
read MSR
receive Xon character(s)/Read of
IIR
read IIR
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C754
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