SC16C754IB80,528 NXP Semiconductors, SC16C754IB80,528 Datasheet - Page 30

• Manufacturer Part Number: SC16C754IB80,528
• Description: IC UART QUAD W/FIFO 80-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C754IB80,528

• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270057528; SC16C754IB80-T; SC16C754IB80-T

Philips Semiconductors
9397 750 11618
Product data
7.11 Divisor latches (DLL, DLH)
7.12 Transmission control register (TCR)
7.13 Trigger level register (TLR)
These are two 8-bit registers which store the 16-bit divisor for generation of the baud
clock in the baud rate generator. DLH stores the most significant part of the divisor.
DLL stores the least significant part of the divisor.
Note that DLL and DLH can only be written to before sleep mode is enabled, i.e.,
before IER[4] is set.
This 8-bit register is used to store the RX FIFO threshold levels to stop/start
transmission during hardware/software flow control.
control register bit settings.
Table 20:
TCR trigger levels are available from 0-60 bytes with a granularity of four.
Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The
programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no
built-in hardware check to make sure this condition is met. Also, the TCR must be
programmed with this condition before Auto-RTS or software flow control is enabled
to avoid spurious operation of the device.
This 8-bit register is pulsed to store the transmit and received FIFO trigger levels
used for DMA and interrupt generation. Trigger levels from 4-60 can be programmed
with a granularity of 4.
Table 21:
Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or
TLR[7:4] are logical 0, the selectable trigger levels via the FIFO control register (FCR)
are used for the transmit and receive FIFO trigger levels. Trigger levels from 4-60
bytes are available with a granularity of four. The TLR should be programmed for
where N is the desired trigger level.
Bit
7-4
3-0
Bit
7-4
3-0
Symbol
TCR[7:4]
TCR[3:0]
Symbol
TLR[7:4]
TLR[3:0]
Transmission Control Register bits description
Trigger Level Register bits description
Description
RX FIFO trigger level to resume transmission (0-60).
RX FIFO trigger level to halt transmission (0-60).
Description
RX FIFO trigger levels (4-60), number of characters available.
TX FIFO trigger levels (4-60), number of spaces available.
Rev. 04 — 19 June 2003
Table 21
shows trigger level register bit settings.
Table 20
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
shows transmission
SC16C754
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N
4
,