SC16C754IB80,528 NXP Semiconductors, SC16C754IB80,528 Datasheet - Page 29

• Manufacturer Part Number: SC16C754IB80,528
• Description: IC UART QUAD W/FIFO 80-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C754IB80,528

• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270057528; SC16C754IB80-T; SC16C754IB80-T

Philips Semiconductors
9397 750 11618
Product data
7.10 Enhanced feature register (EFR)
Table 18:
This 8-bit register enables or disables the enhanced features of the UART.
shows the enhanced feature register bit settings.
Table 19:
Priority
level
1
2
2
3
4
5
6
Bit
7
6
5
4
3-0
Symbol
EFR[7]
EFR[6]
EFR[5]
EFR[4]
EFR[3:0]
IIR[5]
0
0
0
0
0
0
1
Interrupt priority list
Enhanced Feature Register bits description
IIR[4]
0
0
0
0
0
1
0
Rev. 04 — 19 June 2003
Description
CTS flow control enable.
RTS flow control enable.
Special character detect.
Enhanced functions enable bit.
Combinations of software flow control can be selected by programming
these bits. See
page
Logic 0 = CTS flow control is disabled (normal default condition).
Logic 1 = CTS flow control is enabled. Transmission will stop when a
HIGH signal is detected on the CTS pin.
Logic 0 = RTS flow control is disabled (normal default condition).
Logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when
the receiver FIFO HALT trigger level TCR[3:0] is reached, and goes
LOW when the receiver FIFO RESUME transmission trigger level
TCR[7:4] is reached.
Logic 0 = Special character detect disabled (normal default condition).
Logic 1 = Special character detect enabled. Received data is
compared with Xoff-2 data. If a match occurs, the received data is
transferred to FIFO and IIR[4] is set to a logical 1 to indicate a special
character has been detected.
Logic 0 = Disables enhanced functions and writing to IER[7:4],
FCR[5:4], MCR[7:5].
Logic 1 = Enables the enhanced function IER[7:4], FCR[5:4], and
MCR[7:5] can be modified, i.e., this bit is therefore a write enable.
10.
IIR[3]
0
1
0
0
0
0
0
Table 3 “Software flow control options (EFR[0:3])” on
IIR[2]
1
1
1
0
0
0
0
IIR[1]
1
0
0
1
0
0
0
IIR[0]
0
0
0
0
0
0
0
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Source of the interrupt
Receiver Line Status error
Receiver time-out interrupt
RHR interrupt
THR interrupt
Modem interrupt
Received Xoff signal/
special character
CTS, RTS change of state
from active (LOW) to
inactive (HIGH)
SC16C754
Table 19
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